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Matches 601 - 650 out of 6,226

Document Document Title
JP4431134B2  
JPWO2008065869A1
【課題】分周クロック信号のサイクル時間の 変動が小さく、分周クロック信号の最小のサ イクル時間が分周比に応じて拡大される機会 が多く、消費電力やレイアウト面積が小...  
JP4425062B2  
JPWO2008056551A1
分周クロック信号のサイクル時間が一定で、 消費電力やレイアウト面積が小さく、設計・ 検証コストが小さい有理数分周回路を提供す る。分周比がN/M(M、Nは正の整数...  
JP2010041466A
To perform high-precision variable frequency division by setting a variable frequency division ratio in a simple circuit configuration.A 1/P frequency divider 12 subjects an input clock ck to 1/P frequency division. A phase shifter 13 sh...  
JP4416396B2  
JP4418614B2  
JP2010501155A
A high speed, low electric power, and broadband operation are possible, and it provides a frequency synthesis machine including a profit compensation method and a high-speed voltage controlled oscillator (VCO) zone calibration method. Th...  
JP2010011389A
To achieve a frequency divider, in a simple configuration and with high accuracy, such as a baud rate generator that does not use any dedicated oscillator, wherein an error of a frequency to be divided is allowed.As a frequency divider, ...  
JP4390353B2  
JP2009545262A
An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The c...  
JP4383876B2  
JP4386725B2  
JP2009290641A
To provide a DDS circuit capable of improving resolution, without increasing the bit length of a tuning word, and to oprovide an electronic appliance.This DDS circuit has a DDS part 11 to output a sign-wave signal from a tuning word, bas...  
JP2009543470A
The modulus counting-down circuit stage (MDS) includes the 1st and the 2nd stage. MDS receives the number control signal S of modulus 除 which determines by any the MDS shall operate between 2 division mode or trichotomy mode. The stage...  
JP2009283065A
To save power of a clock circuit unit for controlling a DLL (Delay Locked Loop) circuit etc. which requires a start-up time before normal operation.A clock generating circuit is connected to a counter circuit which controls an operation ...  
JP2009278604A
To provide a counter, which reduces propagation time delay of the counter and minimizes data skew.An n-bit counter includes n counter blocks each including: a D-flipflop; a second MUX which selects any one of external data and a second o...  
JP2009278478A
To provide a counter circuit capable of rightly counting a high frequency signal in which hazard or the like may easily occur.A counter circuit includes: a frequency divider circuit 100 for generating frequency-divided clocks LCLKE, LCLK...  
JP4371046B2  
JP2009540762A
The bidirectional direct sequence spectral diffusion half duplex RF modem for transmitting and receiving an analog and digital pulse modulation is provided. The modem incorporates the correlation machine of a SAW base, in order to perfor...  
JP4367342B2  
JP4362430B2  
JP4357692B2  
JP2009246969A
To provide a frequency diverse discrete-time phase-lock device.The frequency diverse discrete-time phase-lock device is provided with an analog section which includes a digital-to-analog converter (DAC) and an oscillator which operates t...  
JP2009246639A
To relax a trade-off relation between a high-speed operation and a wide operating frequency range of an apparatus, in a frequency divider utilizing a current logic type flip-flop circuit.A latch pair part L is divided into a first latch ...  
JPWO2009125580A
A variable delay circuit gives the variable delay according to an analog signal to a reference clock, and generates a delay clock. A phase primary detecting element detects the phase contrast of a delay clock and a reference clock, and g...  
JP2009239764A
To provide a variable frequency divider for outputting an oscillation signal of a frequency band in a desired range and outputting the oscillation signal with restricted harmonic components even if an oscillation signal of wide frequency...  
JP2009231899A
To suppress cycle time variation of an output clock signal frequency-divided by a rational number without requiring a large circuit scale, and to adjust the phase of the output clock signal during frequency division.A clock selection con...  
JP2009231897A
To perform rational number frequency division of an input clock signal and phase adjustment of an output clock signal simultaneously without requiring a large circuit scale.A delay indicated value calculating circuit 101 obtains a delay ...  
JP2009232072A
To provide a PLL circuit capable of quickly making an unlocked state of a frequency of an oscillation signal, while providing the PLL circuit with a plurality of VCOs which have mutually different oscillation frequency bands.The PLL circ...  
JP2009222431A
To provide a coulomb counter which reduces a circuit scale, makes the dynamic range and current resolution of a measuring current variable for optimization and outputs counted values with few errors.The coulomb counter outputs the counte...  
JPWO2007135793A1
制御信号生成回路(2)のカウンタ回路(1 )において、選択回路(3)は選択回路制御 信号(CTR)による制御により、パルス信 号としての信号VSYNCと信号HSY...  
JP2009218877A
To reduce a power consumption in an always-on counter circuit.A counter circuit has a first counter of m bits which counts values of a predetermined bit width to be stored according to an input clock, a clock transmission control circuit...  
JPWO2009116398A
By carrying out the mask of the clock pulse of clock S in a mask circuit (10) according to an inputted mask signal (50), clock B is generated and outputted and it is a mask control circuit (20), It is based on communication timing inform...  
JP2009212736A
To prevent deterioration in imprint characteristics of a ferroelectric capacitor in a semiconductor integrated circuit in which data signals of a latch circuit are held in the ferroelectric capacitor.The semiconductor integrated circuit ...  
JP2009201037A
To implement a self-recovery type or reset-free type 6-, 7-, and 8-frequency division switching circuit that has a small number of elements and reduces a circuit area and power consumption.The circuit comprises edge-trigger type FFs (fli...  
JP2009194560A
To provide a frequency dividing circuit having reduced power consumption.The frequency dividing circuit uses a ring oscillator that connects outputs of a logic inverting circuit in a ring shape, and the logic inverting circuit is operate...  
JP2009188748A
To provide an inverter circuit comprising transistors of the same conductivity type.The inverter circuit includes a NOT logic constitution portion and an output circuit portion and the output circuit portion includes two transistors of t...  
JP2009188749A
To provide an inverter circuit configured such that narrowing of a width of a maximum amplitude of output is reducible.One source/drain region of a first transistor is connected to one source/drain region of a second transistor, the othe...  
JP4309392B2  
JP4305317B2  
JP4304124B2  
JP2009165069A
To improve the accuracy of frequency correction, and furthermore, to miniaturize a circuit scale and reduce power consumption by simplifying a circuit structure.In the frequency correction circuit 5, a counter 10 generates a signal of a ...  
JP2009164929A
To provide a signal generating circuit for generating wide-bandwidth signals while reducing power consumption.The signal generating circuit 1 includes a reference signal source 51 for outputting a reference signal (a), a phase comparator...  
JP2009165064A
To provide a frequency dividing circuit and frequency dividing method capable of synchronizing all frequency divided signals and outputting the frequency divided signals synchronized with the same edge of a clock signal in signals freque...  
JP4299850B2  
JP4298685B2  
JPWO2007099588A1
第1の分周回路と第2の分周回路とを設け、 外部からインジェクションされる2相の外部 クロック(第1の外部クロックおよび第2の 外部クロック)を分周して、位相保証さ...  
JP4292425B2  
JP2009147936A
To provide a dual-modulus prescaler circuit which has a relatively simple structure according to a CMOS technology and operates at a very high frequency.The circuit includes an assembly formed of two D-type flip-flops 12, 13, and two NAN...  

Matches 601 - 650 out of 6,226