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Matches 651 - 700 out of 6,226

Document Document Title
JP4289206B2  
JP2009524319A
It is a circuit for acquiring the output clock signal which has the frequency which is 1 (N is odd number) /N of the frequency of an input clock signal from an input clock signal. A circuit has a plurality of latches constituted as a lat...  
JP2009130760A
To improve flexibility in setting of decimal frequency division, regarding a frequency divider circuit.The circuit includes a clock input terminal; first and second flip-flop circuits to each of which a clock from the clock input termina...  
JP4275844B2  
JP2009124269A
To provide a digital counter, a timing generator, an imaging system, and an imaging apparatus which can reduce the periodic power supply noise, accompanying the counting operation.The digital counter performing count operation by Gray co...  
JP2009124532A
To solve the following problem: when a clock signal becomes a high frequency, a setup time cannot be secured among the clock signal CLK, a chip select signal CS that is a control signal, a read/write signal nRW and a byte write signal EN...  
JP2009094551A
To achieve a counter device which can enhance time precision of a counter and can facilitate timing verification and layout work of logic IC design.The counter device performing count operation by dividing the frequency of a clock signal...  
JPWO2009050854A
Between a collector * emitter was mutually connected in series between the high side power supply and the low side power supply, A logic circuit which operates according to voltage which has the 1st transistor by the side of the high sid...  
JP2009516270A
This indication has described a clock circuit for a memory controller. An indicated circuit generates a feedback clock signal for generating an input clock signal for using a processor clock signal and using it between write-in operation...  
JP2009077415A
To provide a circuit which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude.When an input clock signal CK1 becomes H level, each of TFTs 101, 103 is turned on to settle at ...  
JP4251640B2  
JP4240657B2  
JP2009055597A
To provide a circuit technology capable of finely setting transition timing in a relevant level of a processing objective signal which has a constant or a variable period, and is transited at least in two levels during one period.A timin...  
JP2009049985A
To provide a method for reducing voltage at a bootstrap point in an electronic circuit, and a device using the method.A discharging device is used to reduce the voltage level at the bootstrap point in the electronic circuit such as a shi...  
JP4230665B2  
JP2009033503A
To obtain a frequency divider by which a plurality of output waves are easily and efficiently acquired.The frequency divider is provided with: a frequency division circuit 1 of which the number of frequency division is N (N: an integer 2...  
JP2009017153A
To reduce the time to transfer a count value between circuits which have clock signals with different frequency.In count signals CNT to CNT3 of a gray code counter 11 which is operated by a transmitting side clock signal CLKA, a changed ...  
JP2009502103A
The pure single phase logic clock counting-down circuit (20) constituted so that a clock signal (46) may be Divide (ed) for the increment of 2, 3, 4, or 6 is provided. For a pure single phase logic machine Attached reason, a pure single ...  
JP4199664B2  
JP4197532B2  
JP2008301017A
To provide a digital pulse width modulation apparatus capable of improving the resolution of pulse width modulation without using a clock of a high frequency.The pulse width modulation apparatus using two clocks, i.e. a clock A (100) hav...  
JP2008545321A
The polyphase divider of the present invention is equipped with two or more differential latches connected to the ring. The number of the latches in a ring is equal to the divisor supplied to the number of phases and input clock which sh...  
JP2008545320A
In other bits, a programmable module type digital frequency divider does division of the input frequency by the integer divisor of m bit, and generates output frequency. An integer divisor carries out reinitialization of several meters o...  
JP2008301488A
To provide circuit and a method for programmable integer clock division with 50% duty cycle.The present invention relates to circuits and a method for dividing a frequency of an input signal by an integer divider value. The circuit gener...  
JP2008301325A
To prevent timing of output signals from being deviated in a synchronous type counter circuit by taking layout into account.A counter circuit outputs count values Q0-Q15 of MN bits using M (e.g., four) pieces of N-bit (e.g., 4-bit) synch...  
JP2008545322A
The polyphase divider of the present invention is equipped with two or more dynamic inverters connected to the ring, and the intermediate node on all the ring circumferences is stabilized by the intersection joint latch. A clock input pu...  
JP2008289179A
To accomplish an interlocked counter capable of adjusting a count value at all times in response to an interlocking signal output from another interlocked counter even when interlocked counters not communicating interlocking signals with...  
JP2008282522A
To provide a shift register and a driving method thereof, capable of preventing a node voltage to control an output buffer section from being fluctuated by a parasitic capacitor of a thin-film transistor.In this shift register, each of m...  
JP2008271593A
To provide a prescaler which shortens an operation delay time of an extender unit and is capable of sufficiently ensuring a marginal time, with respect to a malfunction, of a frequency dividing ratio switching operation.A prescaler 21b i...  
JP2008258660A
To provide a Gray code counter which has a reduced delay time of a critical path, then, can be operated fast.A first Gray code bit Q0 is obtained by outputting an output signal Q0o of an RDFF 2 through an RDFF 31 to synchronize with a cl...  
JP2008259228A
To keep continuity of count values when switching count modes in an asynchronous counter circuit capable of switching count modes.In an A/D converting method, between flip-flops 410, three-input and one-output type three-value switching ...  
JP2008251061A
To provide a shift register in which shift register operation can be achieved in a small chip area and which can be operated only by rise (or fall) edge of a clock input.When a control signal CK(36) is low and a control signal CKb(37) is...  
JP4150092B2  
JP4149634B2  
JP2008205760A
To provide a fractional frequency division PLL device capable of improving convenience by reducing the number of parameters to be set and simplifying a circuit, and a control method thereof.For an initial period of an A cycle of a first ...  
JP2008206038A
To provide a frequency divider circuit which has a wide operation frequency range, and is small in size and low in power consumption without using any special switching circuit or control circuit.In the frequency divider circuit includin...  
JP2008196917A
To provide an asynchronous type counter circuit performing verification to a supply pass of a clock signal without complicating a circuit, and improving a failure detection rate.This circuit is equipped with: a plurality of flip-flop cir...  
JP2008199533A
To provide a semiconductor integrated circuit capable of highly accurately inspecting a clock signal even when the clock signal has a high frequency.A semiconductor integrated circuit is provided which is characterized in including a plu...  
JP2008193235A
To provide a phase-compensated clock divider circuit controlling the frequency-divided clock to be always synchronized with a synchronizing signal, and preventing malfunction or delay in operation.The phase-compensated clock divider circ...  
JP2008530651A
The data register (300) used for a computer is equipped with the clock terminal (310) constituted so that a clock signal might be received. Two or more registers (320) are constituted so that data may be stored alternatively. A data inpu...  
JP2008177766A
To simultaneously satisfy a high-speed starting property, a low power consumption property and a low spuriousness under a steady state, and to optimize a parameter controlling a performance.A PLL synthesizer has a constitution changing o...  
JP2008172649A
To share a counter among a plurality of dividers with different division ratios and phases, and to reduce a logical amount and the power consumption of the whole divider circuit by making the division ratio and the phase of the divider i...  
JP2008172512A
To provide a frequency synthesizer capable of realizing frequency division of high precision while suppressing circuit increase, without using a PLL of a conventional configuration, and to provide a clock generation method.The frequency ...  
JP2008160353A
To provide a high-speed programmable synchronous counter for long wording in a high frequency band without using an IC for exclusive use while securing a high timing precision.The high-speed programmable synchronous counter includes a hi...  
JP4114722B2  
JP4111932B2  
JP4111636B2  
JP2008522505A
The phase self-sustaining agile signal generation method, apparatus, and/or a computer program product, Offer a direct digital synthesizer (DDS) clock rate, and the frequency tuning word (FTW) for desired output frequency is offered, Off...  
JP4106842B2  
JP2008141305A
To make shift data of a shift register be reliably latched by a latch circuit without errors even when a reference clock signal is sped up.A load element drive circuit device 10A has a counter 16A for outputting an enable signal enable o...  

Matches 651 - 700 out of 6,226