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JP3714875B2 |
To provide a gray code counter, with which skip counting is enabled and the number of bit transitions in skip counting is two at all the time. This gray code counter is provided with a gray code counter 2 in the configuration of 5 bits f...
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JP3711455B2 |
To provide a high-speed multi-bit binary counter circuit. In a multi-bit counter circuit in which 1-bit counter circuits 1 are coupled in series, the 1-bit counter circuits 1 are separated into at least one lower order 1-bit counter 1 ta...
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JP2005303884A |
To provide a flip-flop circuit in which power consumption can be reduced and a malfunction can be suppressed.In a flip-flop circuit comprised of a data input/output section 10, a clock input section 11 and a current supply section 12, bi...
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JP2005293817A |
To provide a shift register capable of preventing the fluctuation of the voltage of a node for controlling an output buffer part caused by the parasitic capacitor of a thin-film transistor, and its driving method.This shift register is p...
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JP3707203B2 |
To provide a frequency divider where a clock signal is frequency- divided at frequency division ratios including a half cycle of the clock signal. The frequency divider is made up of a 1/(2n+1) frequency divider 1, a duty adjustment devi...
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JP2005286797A |
To provide a signal generating circuit capable of realizing the circuit layout independently of timing of produced pulses.A shift register 10 has a plurality of stages of registers 11 to 1n, and transmits a start pulse SP generated by a ...
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JP2005277875A |
To provide a pulse swallow type variable divider which is faster than before even using the same manufacturing technology with conventional one, with no use of a device of fast operation and a device of high power.The divider comprises a...
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JP2005277665A |
To shorten the lockup time by reducing reference spurious radiation of a PLL synthesizer.The frequency of a signal inputted to a main counter 12 and a swallow counter 11 is halved by inserting a half fixed frequency divider 10 to the pos...
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JP3703347B2 |
To provide a frequency divider circuit from which a frequency division ratio of 2 over odd numbers with a simple circuit configuration. The frequency divider circuit comprises a flip-flop multi-stage circuit G consisting of n-sets of fli...
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JP3696899B2 |
PURPOSE: To lead out lock detection signals by providing first input for receiving a program integer and a latch circuit for leading out a latch integer. CONSTITUTION: A phase detector 14 generates UP or DOWN signals by the phase relatio...
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JP3696004B2 |
To provide a semiconductor circuit wherein respective outputs of cascaded flip-flops never reach unintended values. This semiconductor circuit is constituted by cascading (n) register circuits REG0 to REGn-1. Each register circuit select...
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JP3688683B2 |
To generate a precise fraction frequency division signal irrespective of precision of a decimal part of a frequency-divided number. A cumulative adder 7 performs cumulative addition of a decimal value f set in an f setting part 8 in resp...
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JP2005223829A |
To provide a fractional frequency divider circuit which reduces its circuit scale and outputs a clock of a duty ratio 50%, and data transmission apparatus having the frequency divider circuit.A fractional frequency divider circuit includ...
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JP3682765B2 |
To provide a frequency divider that is operated at a high speed. The frequency divider comprises a latch circuit L101, an inverting circuit IV102, and an IV105 that is in a closed loop connection. The latch circuit L101 consists of a tra...
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JP2005198296A |
To provide a numeric counter oscillator (NCO) of high-level accuracy for making a frequency resolution more flexible.An NCO has a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for rec...
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JP2005198339A |
To provide a programmable frequency divider for a phase lock loop having a latch circuit with a first input receiving a program integer and an output deriving a latch integer.A phase lock loop monitors a first digital signal and derives ...
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JP2005198164A |
To provide a PLL synthesizer for adopting a fractional frequency division system employing a delta sigma circuit for realizing a low consumed current without deteriorating the characteristic.A period shared by "H" levels is equal to a pe...
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JP3666078B2 |
To provide a circuit by which plural frequencies can be obtained and which can be used for the speed control of a pulse motor and the like by inverting the logic value of an output signal when a frequency division counter value is matche...
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JP3666352B2 |
To solve a problems that a malfunction takes place because a clock cycle becomes so short that internal delay can not follow when noise is mixed with a clock in the conventional frequency dividing circuit and that only noise below fixed ...
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JP2005159737A |
To speed up operating speed in a frequency dividing circuit in a variable frequency dividing circuit effective to a circuit that has a number of dividing stages and requires high-speed operation.There are provided a shift register compos...
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JP3657191B2 |
To provide an up/down gray code counter whose circuit scale can be made small. This up/down gray code counter is provided with an up count gray code counter 3 for performing only up counting and a most significant bit data selecting mean...
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JP3654153B2 |
To provide a clock signal generator that can reduce power consumed by its circuit sections not substantially requiring operations. A frequency divider side selection output means 35 stops the operation of a frequency divider circuit 24 a...
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JP2005141885A |
To provide an address control circuit which is reduced in circuit size and can perform high-speed operation.The device is equipped with a first counter 11a and a second counter 11b. Based on a switching signal SS for switching whether an...
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JP3649874B2 |
To provide a frequency divider which performs the division of frequency that is not equal to an integral multiple of an input signal. This divider 10 can perform both 1/X division and 1/(X+1) division (X: an integer). The frequency of an...
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JP3649640B2 |
To provide a semiconductor resistor element where power consumption in a CMOS semiconductor integrated circuit can be reduced in stands by. When a system shifts to standing by, the application of an input voltage to a temporary storage e...
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JP2005508577A |
A circuit generates an output signal whose frequency is lower than the frequency of an input signal. In an example embodiment, there is a chain of frequency dividing cells. Each of the frequency dividing cells has a pre-defined division ...
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JP3633299B2 |
To take out a tripartite output signal of a duty factor 50% from an inputted signal. A signal inputted from outside and another signal are inputted to a multiplier circuit 2, and a signal taken out from it is inputted to an amplifier 3 t...
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JP3631573B2 |
To digitally reduce an electromagnetic interference noise level by obtaining a first signal from a base signal by means of a digital system so as to execute modulation, obtaining a modulation reference signal which is fluctuated between ...
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JP3631375B2 |
To provide a frequency divider capable of enlarging a frequency range and performing a high-speed operation by changing a free-run frequency without largely changing an output signal amplitude. This frequency divider is composed of two b...
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JP3629050B2 |
PURPOSE: To increase the operation speed by transmitting a carry signal by combination of gate means. CONSTITUTION: A carry signal CAR1 is transmitted through two stages of gate delay where a signal CAR0 passes a NAND gates 51 through a ...
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JP2005064995A |
To suppress jitter occurring internally without increasing power consumption.A synchronization compensation circuit 1-2 is provided on the poststage of a frequency divider 1-1. A master clock is inputted to a branch of the synchronizatio...
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JP2005057463A |
To provide a two-modulus prescaler circuit which operates with low power consumption.In the prescaler circuit, each of 1st to (n-2)th D flip-flops is equipped with a 1st latch circuit having a couple of MOS switches, a 1st differential p...
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JP3624690B2 |
To provide inexpensively a pulse arithmetic processing unit of a very high speed, where an 'integer of the unity or over within a range which is not larger than the denominator of a frequency division ratio' can be set, even to a numerat...
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JP2005045507A |
To provide a non-integer frequency divider that can be constituted by combining the circuits with simple functions and whose frequency division ratio can simply be set.This non-integer frequency divider has an adder 11 which adds a 1st s...
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JP2005037169A |
To provide a semiconductor integrated circuit allowing knowledge of power consumption of each functional block.This semiconductor integrated circuit has: first to third signal processing circuits 11-13 respectively operating in synchroni...
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JP3618301B2 |
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JP3618918B2 |
To reduce a signal amount on the whole by decreasing the number of input signals. As for an A, a B, and a C signal of '1' and '0' outputted from an input circuit 1, a state change decision circuit 3 decides whether or not the B and C sig...
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JP3612886B2 |
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JP2005012515A |
To provide a variable frequency divider by eliminating a path with a greater capacity load such as a critical path and to achieve low power consumption.A feedback path 207 is formed between an output of a fixed frequency divider 205 and ...
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JP3609601B2 |
To easily confirm whether timer counter operation is normal or abnormal by incorporating a function for detecting the counter operation being abnormal according to the result of logical operation between the time of the timer counter cir...
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JP2004363821A |
To provide a frequency-dividing circuit that can obtain various numbers of frequency division with the same constitution and perform stable frequency division even when an input reference clock is fast.The frequency-dividing circuit is e...
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JP2004364105A |
To improve the maximum operation frequency of a prescaler circuit 1 without depending on the process of an element.Flip-flops FF1 to FF3 apply 1/4-frequency division to a clock inputted to a clock terminal by feedbacking the output of th...
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JP3601961B2 |
A dual-modulus prescaler (100) has improved performance for high-speed operation. A timing signal is developed from a flip flop circuit (106) two and one-half clock cycles before the last stage of the prescaler is clocked. The timing sig...
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JP2004537188A |
A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") transmits a plurality of clock phases to a clock divider circuit which produces the desired n...
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JP2004336232A |
To generate a frequency divided clock usable for the reference clock, even when the ratio of an oscillation frequency to a divided frequency is not an integer one.The frequency division circuit comprises a crystal oscillator circuit 1 fo...
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JP2004328301A |
To provide a variable frequency divider capable of performing a more stable high-speed operation without increasing the bit width of a counter.N1 is loaded as an initial value on a binary down-counter 12 when a count value becomes -N2. A...
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JP2004328300A |
To provide a variable frequency divider capable of performing a stable high-speed operation.A prescaler 10 switches a frequency dividing ratio according to a level of a frequency dividing ratio control signal PCTR outputted from a swallo...
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JP2004289422A |
To reduce the power consumption and a required number of FF circuits.The frequency divider circuit is provided with: a high speed frequency divider circuit 11 comprising a high speed operating device, applying 1/M frequency division to a...
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JP2004531107A |
The present invention provides a synthesiser having a divide circuit implemented using only a single counter along with a decoder. This allows for a method of designing a plurality of divide circuits which each use the same single counte...
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JP3572908B2 |
There is disclosed a frequency divider that operates at an improved operating speed and provides frequency division given with a frequency division ratio of N, where N is an odd number. The frequency divider comprises first, second, and ...
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