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Patent Searching and Data


Matches 701 - 750 out of 6,211

Document Document Title
JP4077483B2  
JP2008085543A
To provide a counter circuit capable of increasing the number of countable counts without increasing a hardware circuit scale.An n-bit hardware counter 12 sequentially counts output signals of a pulse string generating means 16 for gener...  
JP2008510339A
A frequency division circuit is equipped with a pair of multistate circuits (MSCA, MSCB). Each multistate circuit is switchable through the cycle of a state (SA (1), . . , SA (N) ;SB (1), . . , SB (N)). One multistate circuit (MSCA) is s...  
JP2008510428A
A counter has a dividing coefficient which can be chosen using two or more multiplexers. This counter includes an inverter and the concatenation delay stage which has the stage delay which can be chosen. The inverter has connected the st...  
JP2008509590A
The frequency divider equipped with the 1st latch circuitry (10) and 2nd latch circuitry (10') by which intersection combination of the 2nd latch circuitry (10') is carried out in the 1st latch circuitry (10). Each latch (10, 10') contai...  
JP2008509589A
The divider which has odd divisors has a clock input for receiving a periodic clock signal (Ck) with frequency, and the 1st even number is equipped with the binary counter (10) which has even divisors smaller than the divisor of the abov...  
JP2008071467A
To provide a latency counter equipped with a frequency detector suited to both of high-frequency and low-frequency operations, and its related method.The latency counter includes a clock delay module for delaying an input clock based on ...  
JP4063001B2  
JP4044819B2  
JP4044020B2  
JP2008017287A
To provide an inexpensive RC calibration circuit in which a calibration time is short.This RC calibration circuit generates a frequency-division signal VIN by dividing frequency of a reference clock signal RefCLK into two, and charges a ...  
JP2008005446A
To solve the problem of increase in size and cost of a frequency divider for outputting a plurality of output signals which differ in division ratios requires a plurality of frequency divider circuits more than the number of division rat...  
JP4028147B2  
JPWO2007135793A
In a counter circuit (1) of a control signal generation circuit (2), by control by a selection circuit control signal (CTR), a selection circuit (3) chooses a predetermined thing of signal VSYNC as a pulse signal, and the signals HSYNC, ...  
JP4015232B2  
JP2007300450A
To provide a clock-generating circuit for generating a plurality of clocks at low cost by saving power consumption without having to use a PLL, and to provide an information-reproducing device, and an electronic apparatus, etc. The clock...  
JP2007294484A
To improve the characteristics of a semiconductor integrated device for processing high-speed signals. Flip-flop circuits 21-25 for composing a prescaler 16 and NAND circuits 26-29 are arranged in two parallel rows on a semiconductor sub...  
JP3998217B2  
JP2007529179A
The frequency divider (2) which has a section (21*27), Depending on the control signal (c) produced from a next section depending on an adjustment signal (p), with the number which can be adjusted, It has the basic section (21, 22, 23) o...  
JP3993717B2  
JP2007266820A
To provide a register circuit and electric equipment using the register circuit, capable of increasing noise tolerance without delaying an output response to a regular signal input. A register circuit 1 includes a register portion 10 hav...  
JP2007528657A
As for the present invention, this divider has a latch (10) and the 2nd latch (20) of the 1st about a divider, and intersection combination of the 2nd latch (20) is carried out with the 1st latch. The 1st latch (10) has a clock input whi...  
JP2007266741A
To provide a prescaler with broadband. The prescaler 33 is provided with a buffer section 41 and a counter 43. The buffer section 41 includes: a first stage circuit 52 comprising a plurality of inverter circuits 52a to 52c different in d...  
JP2007267034A
To provide a high speed dynamic frequency divider which is to be operated in high speed with low power consumption. The frequency divider includes a buffer 30, a function selector 31, and an inverter 32. An output of the function selecto...  
JPWO2005018094A1
半導体集積回路装置1において、シフトレジ スタSR1のフリップフロップFF64の出 力とシフトレジスタSR2のフリップフロッ プFF65の入力との間を電気的に接離...  
JP2007259125A
To provide a clock frequency divider which can continuously operate without causing deadlock even when a user makes a mistake in setting of clock frequencies (division ratio) of each clock area in a system LSI having a large scale and a ...  
JP2007243617A
To provide a differential output frequency divider circuit in which a CMOS inverter is used and a delay difference between differential signals does not occur. The frequency divider circuit for dividing a clock signal to output it is pro...  
JP2007233968A
To provide a device that can ON/OFF-control an SSC (spread spectrum clock) function and can implement a smooth ON/OFF transition of the SSC function without any transient frequency changes. A control circuit 3 for generating a phase cont...  
JPWO2007099588A
The 1st part circumference way and the 2nd part circumference way are provided, the external clock (the 1st external clock and 2nd external clock) of 2 phases by which injection is carried out from the outside is 分周 (ed), and the clo...  
JP2007221587A
To set the duty ratio of the output signal of a variable frequency divider to an arbitrary ratio. The variable frequency divider for outputting a frequency-divided clock by dividing an input clock by a preset frequency division ratio inc...  
JP2007214960A
To obtain low power consumption while operation speed is kept unchanged. In a toggle type flip-flop circuit (TFF), each signal of an output terminal (out) and an inverse output terminal (outb) latched at latch portions 22A, 22B are conve...  
JP2007215213A
To provide a method for multiple-phase clock generation. In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired ...  
JP2007207413A
To provide a semiconductor device where characteristic deterioration of each transistor is suppressed without making operation instable. In a non-selection period, turning on of a transistor every fixed interval supplies power source pot...  
JP2007522712A
The phase locked loop composition containing the antenna coil, the antenna resonance capacitor, the rectifier, the voltage control ring oscillator, phase detector, and loop filter which cause a differential input signal is used for an un...  
JP2007202151A
To provide an integrated circuit for asynchronous serial data transmission with a bit length counter. The present invention relates to an integrated circuit (7) for asynchronous serial data transmission having a structure for constitutin...  
JP2007521713A
The counter for compounding the clock signal equipped with the minimum jitter, In order to determine whether the trigger of the rising edge of an output clock must be carried out by the rising edge or falling edge of an input clock signa...  
JP2007194976A
To provide an elastic store circuit capable of correcting phase difference between input and output timings without stopping input data or output data. A phase stability monitoring portion 19 monitors phase difference and stability of a ...  
JP2007173971A
To provide an analog frequency divider having a wide operational frequency bandwidth.A parallel circuit of an inductor L1 and a resistor R1 is connected as a load between a power supply voltage VDD and the drain of an MOS transistor TR1,...  
JP2007166624A
To provide a counter capable of outputting a count value after holding the count value and a phase locked loop (PLL) including the counter.The present invention relates to a counter that may include a selection unit and a counting unit. ...  
JP2007515821A
The present invention indicates the frequency divider using a half add function. This frequency divider has an AND gate circuit which takes in the total output of the latch circuitry which has one half add function in each beam, and this...  
JP2007133527A
To make it possible to set the frequency-division rate of each clock signal, and to switch the frequency-division rate of the clock signal based on the set frequency-division rate to output a clock signal in a clock generation circuit fo...  
JP3956768B2
To solve a problem that a frequency not suitable for a task is often generated with a clock generator which generates clocks of a plurality of frequencies, and that useless power is consumed in that event. The clock generator includes: a...  
JP3958322B2
To improve both of rising characteristics and falling characteristics of an output signal in a flip-flop, and to reduce the signal delay of a shift register constituted by this flip-flop. A latch unit 22 has a latch circuit for latching ...  
JP3952576B2
To a provide a controller capable of improving processing efficiency without using a software timer and performing high-speed processing. Count time data T1 are inputted from a CPU 1 to a programmable counter circuit 21, and output data ...  
JP2007116257A
To solve a problem of a conventional differential latch that an unstable operation begins when an input amplitude gets smaller due to the effect of a high speed operation or the like.A plurality of threshold values of longitudinally stac...  
JP3949995B2
To provide a counter circuit capable of forming a plurality of pulse signals of different periods, without increasing the circuit scale. The counter circuit comprises an initial value register single port RAM 5, having initial value regi...  
JP2007102936A
To provide a semiconductor storage device having a latency counter which can perform precise synchronization between latching of an internal command and reading in a latch circuit, and can count latency with precision.In the semiconducto...  
JP3940877B2
To provide a pulse output device that eliminates the need for error correction of an oscillation frequency and can realize synchronization with an execution period of (input data from) an external processing unit, such as a CPU and that ...  
JP2007097148A
To widen a dividable frequency band without performing variable control of a load circuit.A master stage 101 comprises: a differential circuit including a transistor 1 and a transistor 2; a differential circuit including a transistor 3 a...  
JP2007509561A
This frequency divider has the 1st flip-flop (M1, M2, M3, M4) with the 1st clock input unit which receives a clock signal. The above-mentioned flip-flop -- further -- the [the 1st set input unit (Q4) and] -- it has 1 non-inverted output ...  

Matches 701 - 750 out of 6,211