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Patent Searching and Data


Matches 751 - 800 out of 6,225

Document Document Title
JP2007202151A
To provide an integrated circuit for asynchronous serial data transmission with a bit length counter. The present invention relates to an integrated circuit (7) for asynchronous serial data transmission having a structure for constitutin...  
JP2007521713A
The counter for compounding the clock signal equipped with the minimum jitter, In order to determine whether the trigger of the rising edge of an output clock must be carried out by the rising edge or falling edge of an input clock signa...  
JP2007194976A
To provide an elastic store circuit capable of correcting phase difference between input and output timings without stopping input data or output data. A phase stability monitoring portion 19 monitors phase difference and stability of a ...  
JP2007173971A
To provide an analog frequency divider having a wide operational frequency bandwidth.A parallel circuit of an inductor L1 and a resistor R1 is connected as a load between a power supply voltage VDD and the drain of an MOS transistor TR1,...  
JP2007166624A
To provide a counter capable of outputting a count value after holding the count value and a phase locked loop (PLL) including the counter.The present invention relates to a counter that may include a selection unit and a counting unit. ...  
JP2007515821A
The present invention indicates the frequency divider using a half add function. This frequency divider has an AND gate circuit which takes in the total output of the latch circuitry which has one half add function in each beam, and this...  
JP2007133527A
To make it possible to set the frequency-division rate of each clock signal, and to switch the frequency-division rate of the clock signal based on the set frequency-division rate to output a clock signal in a clock generation circuit fo...  
JP3956768B2
To solve a problem that a frequency not suitable for a task is often generated with a clock generator which generates clocks of a plurality of frequencies, and that useless power is consumed in that event. The clock generator includes: a...  
JP3958322B2
To improve both of rising characteristics and falling characteristics of an output signal in a flip-flop, and to reduce the signal delay of a shift register constituted by this flip-flop. A latch unit 22 has a latch circuit for latching ...  
JP3952576B2
To a provide a controller capable of improving processing efficiency without using a software timer and performing high-speed processing. Count time data T1 are inputted from a CPU 1 to a programmable counter circuit 21, and output data ...  
JP2007116257A
To solve a problem of a conventional differential latch that an unstable operation begins when an input amplitude gets smaller due to the effect of a high speed operation or the like.A plurality of threshold values of longitudinally stac...  
JP3949995B2
To provide a counter circuit capable of forming a plurality of pulse signals of different periods, without increasing the circuit scale. The counter circuit comprises an initial value register single port RAM 5, having initial value regi...  
JP2007102936A
To provide a semiconductor storage device having a latency counter which can perform precise synchronization between latching of an internal command and reading in a latch circuit, and can count latency with precision.In the semiconducto...  
JP3940877B2
To provide a pulse output device that eliminates the need for error correction of an oscillation frequency and can realize synchronization with an execution period of (input data from) an external processing unit, such as a CPU and that ...  
JP2007097148A
To widen a dividable frequency band without performing variable control of a load circuit.A master stage 101 comprises: a differential circuit including a transistor 1 and a transistor 2; a differential circuit including a transistor 3 a...  
JP2007509561A
This frequency divider has the 1st flip-flop (M1, M2, M3, M4) with the 1st clock input unit which receives a clock signal. The above-mentioned flip-flop -- further -- the [the 1st set input unit (Q4) and] -- it has 1 non-inverted output ...  
JP3937686B2
To provide a ripple counter that corrects the count between circuits at different operating speed on the basis of prescribed correction data, and a counter correction method in the ripple counter. The ripple counter is provided with a bi...  
JP2007508733A
Phase switching dual modulus プリスケーラ which has a dual modulus divider is brought about. The above-mentioned divider has the first and the second two frequency divider (A; B), two frequency dividers (B) of the above second are ...  
JP2007508767A
The divider of a high frequency clock signal contains the shift register (8) which has a cell (10*13) which memorizes each bit of an initial word, Series connection of the above-mentioned cell is carried out into a loop (14), and the abo...  
JP3935901B2
To provide a programmable low-power high-frequency divider circuit. A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter sta...  
JP2007074636A
To easily obtain outputs of an odd number division with 50% duty ratio and an even number division by conducting a change-over of them and to select the odd number division ratio furthermore.A feedback signal generating part 200 where th...  
JP3930773B2
To provide a frequency correction circuit for precisely correcting a clock signal of an oscillation frequency with a simple structure without adjusting the oscillation frequency in an oscillation circuit. Into the TBC(time-base counter)1...  
JP3913231B2
To generate multiple clock signals so as to establish distinct phase relations between clock signals having different frequencies. A device adapted to supply a plurality of clock signals is obtained. The device is provided with a pair of...  
JP2007502409A
A position detection device equipped with the photon detection element array which has a parallel arithmetic processing part constituted so that the segment which has the maximum intensity by comparing the output value (OV) from n segmen...  
JP2007019840A
To provide a PLL frequency synthesizer, a semiconductor integrated circuit, and a communication device which allow the reduction in power consumption and have high stability of operations.In the PLL frequency synthesizer, a variable freq...  
JP3903607B2
To accurately read the data of pulse counters and pulse interval counters even when a clock frequency is high. The pulse counters 13 counting an inputted pulse detecting signal detected by a pulse detecting circuit 11 in a fixed period a...  
JP3868505B2  
JP3901607B2
To provide a signal processing apparatus with a small circuit scale, a non-integral frequency divider and a fractional N PLL (phase lock loop) synthesizer having the same. An adder 8 and a delay device 10 constitute a 9-bit accumulator, ...  
JP3901999B2
To save labor for temporarily preparing a frequency divided signal of which duty ratio is not 50 after doubling a clock signal in odd frequency division, and then dividing the frequency of the prepared frequency divided signal into half ...  
JP2006340133A
To provide a semiconductor integrated circuit which can start outputting of a clock signal quickly without starting a frequency division fault in a frequency dividing circuit when an output shut down is canceled by an output control sign...  
JP3888236B2
To provide a program counter circuit which facilitates starting of a program from an arbitrary address other than 0th. In a multiplexer 50, when a select signal CMX is "0", data "00000" of a first input terminal are outputted as preset d...  
JP3884553B2
To generate a clock which has a 50% duty cycle and cycles that are an odd multiple of those of an input clock by comparing the count value of the input clock with a 1st divisor obtained by dividing an input divisor by two and a 2nd divis...  
JP2006318002A
To provide a clock frequency-dividing circuit which is capable of high-speed and stable switching and reducible in circuit scale.In synchronism with timing of variation of a frequency-division clock signal to a low level, the clock frequ...  
JP2006319446A
To provide a frequency-dividing circuit for stably generating a pulse signal for generating a sawtooth wave signal having a frequency of one third of the frequency of an input signal.A T-flip-flop 21 inverts an output state in synchroniz...  
JP2006314134A
To provide a high-speed counter circuit which produces digital counts, with a plurality of bits to control the timing of operations in a memory device.A counter circuit includes a series of registers driven by two phase shifted clocks. A...  
JP3866070B2
To obtain a display device provided with a dynamic ratioless shift register operating stably and permitting to increase a degree of freedom for design. This is a dynamic ratioless shift register provided with thin film transistors of whi...  
JP2006279962A
To manufacture a PLL circuit with proper examination step flow and a minimum examination time.The present invention relates to a system and method for configuring a dividing ratio of a phase-locked loop (PLL) which does not require the p...  
JP2006277789A
To provide a shift register which can be constituted of single conduction type transistors and in which a shift direction can be reversed and a display apparatus in which the shift register is used for a drive circuit of a pixel array.Wh...  
JP3830940B2  
JP2006270438A
To provide a clock-generating circuit capable of frequency conversion, using a simple configuration.The clock-generating circuit which generates a clock of 12 MHz in frequency, from a clock of 13.5 MHz in frequency masks one clock from a...  
JP2006269002A
To provide a shift register circuit, a display apparatus, and portable equipment provided with the display apparatus in which further miniaturization and weight-reduction are achieved and the further reduction of power consumption can be...  
JP2006268617A
To provide a clock generation circuit capable of generating clock of Duty 50%.A clock generating circuit 31 for dividing the frequency of a multiplication clock based on frequency dividing ratio data, comprises a frequency dividing ratio...  
JP3830526B2  
JP2006522527A
n dividing process is performed by a 4/n scale process (110, 210, 310) and 4 dividing process (120, 220, 320) of following. A rectangular input clock makes a 4/n scale process easy according to a clock phase selection process. By incorpo...  
JP3857916B2
To make it possible to be operated with a small signal amplitude and reduce power consumption in a two-modulus prescaler circuit available for a frequency synthesizer or the like. The prescaler circuit is provided with n pieces of (n≥3...  
JP2006254451A
To synchronize two clocks with each other in initiation in a certain specific circuit.An apparatus has a frequency divider accepting a clock 106. The frequency divider 104 is selectable between an N divide factor and an M divide factor v...  
JP2006245794A
To provide a frequency divider capable of attaining high frequency operations with low power consumption.A latch circuit acting like a unit element of the frequency divider is configured with an ECL logic circuit provided with inductors ...  
JP2006244616A
To provide a shift register unit in which power consumption is reduced, the number of elements is decreased, and a required chip region is reduced, and two output pulses can be generated successively.In the shift register unit in which t...  
JP2006230017A
To provide a frequency division circuit for suppressing the amount of jitters that arise with an output signal.This circuit comprises a circuit module 3 that activates series-connected D-FF7, 9 and 11, by using a reference clock signal a...  
JP2006229957A
To provide an automatic initialization type frequency divider for a high-frequency clock.A frequency divider is a closed loop system having a re-circulation storage element 100, at least one feedback storage element 102, and an end stora...  

Matches 751 - 800 out of 6,225