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Patent Searching and Data


Matches 801 - 850 out of 6,226

Document Document Title
JP2006229957A
To provide an automatic initialization type frequency divider for a high-frequency clock.A frequency divider is a closed loop system having a re-circulation storage element 100, at least one feedback storage element 102, and an end stora...  
JP3810437B2  
JP2006203390A
To provide a counter capable of high-speed counting without increasing a circuit scale.In the counter 41 incorporated in a laser scanning type optical measurement apparatus, low-order bit data D0-D2 are generated in a phase split system,...  
JP2006203664A
To make phase noise of an output signal small in a fractional PLL frequency synthesizer.A series of integer dividing frequency of a frequency dividing circuit in a fractional PLL is stored in a memory device beforehand, is read out seria...  
JP3833547B2
To provide a variable circuit whose configuration can be easily modified to create an arbitrary Johnson counter, after creating the circuit. At each input side of JK flip-flop sections 11-14, one connection selected from a twist connecti...  
JP2006196973A
To provide a variable frequency divider with a high degree of design freedom against capturing of erroneous data to a programmable counter in a particular input timing of a load enable signal and capable of early outputting a desired fre...  
JP2006197367A
To provide a counter circuit capable of reducing power consumption and a semiconductor device using it.The counter is equipped with counters (F0-F2, G1-G4) which have multistep flip-flops for counting clock signals, and a mask circuit (F...  
JP2006197620A
To improve followup performance of a control oscillation section in a digital phase-locked loop circuit.In the digital phase-locked loop circuit, a second frequency divider 18 divides a predetermined master clock into 1/N stages accordin...  
JP3829676B2
To realize a frequency divider capable of increasing an operation frequency to a counter operation frequency inside a variable frequency divider. A frequency dividing data generating section 12 consists of ring counters 121-124, and data...  
JP2006191265A
To provide a clocked inverter circuit preventing occurrence of punch-through data, contributing to low power consumption, and reducing the circuit scale, and also to provide a shift register, a scanning line drive circuit, a data line dr...  
JP2006191264A
To provide a clocked inverter to which a delay function is attached.The clocked inverter 11n is provided with an inversion circuit 20, a first circuit 21, and a second circuit 22. When the first and second circuits 21, 22 are active, pow...  
JP2006191530A
To provide a counter circuit for controlling an off-chip driver, capable of changing a DC (or AC) output current value of the off-chip driver, in response to the variations in process characteristics of a PMOS and an NMOS in a wafer stat...  
JPWO2004105247A1
固定分周器(305)の出力(310c)と 反転/非反転器(304)の制御端子(31 0b)との間にフィードバックパス(307 )を形成する。フィードバックパス(3...  
JP3825722B2
To provide a semiconductor circuit device for making it unnecessary to synchronously arbitrate an interface between a block synchronizing with a source clock and an integrated circuit part operating with a frequency different from the so...  
JP3821441B2
To provide a prescaler circuit which has enlarged margin of delay time at which a malfunction occurs, when switching the frequency dividing number. The circuit is provided with a frequency dividing switching part 59a, comprising first to...  
JP3821819B2
To provide a logic circuit, an analog/digital (A/D) conversion circuit and the like with a small number of elements by utilizing a capacitive coupling circuit. In the A/D conversion circuit including an input terminal to which an analog ...  
JP2006174197A
To provide a clock creation circuit, and its method which can create an output clock signal CLKreq which has a frequency "freq" between a frequency fref/A of a demultiplied clock signal CLK1 and a frequency fref/(A+1) of a demultiplied c...  
JP2006174098A
To reduce a circuit scale in a frequency divider circuit capable of generating a dividing clock at an arbitrary division ratio.The frequency divider circuit comprises a counting circuit and a comparison circuit. The counting circuit coun...  
JP2006165931A
To provide a frequency-dividing circuit for easily generating a frequency-division clock signal whose frequency-division ratio is not an integral value for an original oscillating clock signal and communication equipment equipped with th...  
JP2006157121A
To provide a counter circuit operable at a higher clock frequency.The counter circuit, in order to attain the operation at the higher frequency, is configured with a first and second counter circuits 1, 2 for counting the number of input...  
JP2006157849A
To provide a frequency divider or the like which can divide the frequency of a clock signal by a desired frequency division ratio.A frequency divider is provided with a first circuit 10, activating an enable signal according to the frequ...  
JP3812141B2
To provide the frequency divider having small power consumption and the PLL circuit using it. A capacitor 44 is so charged by a master slave circuit B as to accumulate electric charges through an analog switch circuit 40 or discharges el...  
JP2006148807A
To generate a clock signal of a desired frequency by dividing a frequency of the clock signal in an arbitrary frequency dividing ratio.An adder 108 inputs a numerator setting value N and the last added result from a register 109 and outp...  
JP2006148891A
To provide a delay synchronous loop capable of generating multiple clock signals having different phases from one another.The delay synchronous loop is provided with a phase detector 12 for detecting a phase differential between the cloc...  
JP2006148269A
To provide a highly reliable bootstrap circuit by reducing variation in potential caused by bootstrap effect.The bootstrap circuit comprises a transistor 1 outputting a voltage, a bootstrap capacitor 4 provided between the gate and sourc...  
JPWO2004057760A1
本発明は、インバータの入力部をインバータ の閾値電位にし、インバータの入力部に容量 手段を介してCK信号を入力することで、C K信号は増幅され、その増幅されたCK...  
JP2006115234A
To provide a frequency division circuit of which the operation speed can be increased.A master circuit 10 comprises a differential amplification circuit 10a for taking in an output of the frequency division circuit in response to a clock...  
JP2006513507A
It is a digital counter (for example, Fig. 1) using nonvolatile memory (12, 14, 16, 18, --) as a storage cell, A storage cell is subdivided by two groups and two groups are the counters for realization of the rotary counter (20, 22) whic...  
JP2006101168A
To provide a frequency synthesizer which is capable of shortening a lockup time and reducing power consumption simultaneously by reducing the lower limit of the setting range of the total number of division frequencies and increasing a r...  
JP2006101483A
To provide a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sensor pins.The solid s...  
JP3766024B2  
JP2006094478A
To provide a frequency divider capable of reducing a probability of output error occurrence caused by circuit configuration by making common a voltage/current converting unit that causes phase error and/or amplitude error generation.The ...  
JP2006067411A
To provide a modulation circuit which reduces jitter, or a phase synchronization circuit with a division frequency equal to or less than a decimal point using the modulation circuit, or an interface device using the phase synchronization...  
JP2006067190A
To provide a clock-generating circuit outputting a frequency-dividing clock at a desired fractional multiplication and inhibiting increases in the area and power.The clock-generating circuit has a plurality of steps of delay circuits 10A...  
JP2006054806A
To provide a prescaler circuit which has enlarged margin of delay time at which a malfunction occurs, when switching the frequency dividing number.The circuit is provided with a frequency dividing switching part 59a, comprising first to ...  
JP3769909B2
To output a pulse signal having a frequency value which is not the cumulation value of '2' and to prevent inner constitution from becoming complicated by sequentially accumulating the frequency value in an addition circuit whenever a spe...  
JP2006050288A
To provide a shift circuit which can reduce power consumption since leakage in the off-state of a level shift section can surely be prevented and is resistant to dispersion in transistor characteristics by adopting a circuit configuratio...  
JPWO2006016580A
A master latch (1) is constituted from a static circuit, and a slave latch (2) consists of dynamic circuits. Thereby, compared with a case where a slave latch is constituted from a static circuit, the number of circuit elements can be re...  
JP2006050289A
To provide a shift register circuit which can reduce the power consumption and is resistant to dispersion in transistor characteristics and to provide a display apparatus on which the shift register circuit is mounted as part of its driv...  
JP3746124B2  
JP3767159B2
To realize a counter for counting at different number of bits depending on the state of peripheral circuit by providing an n-bit counter for counting the output from a counter control circuit received as preset signal. A counter control ...  
JP2006024350A
To provide a shift register wherein high image quality of a display device can be maintained for a further long time by enhancing reliability of a driving circuit of a display panel without obstructing miniaturization of the driving circ...  
JP2006005954A
To provide a gray code counterby which an interlaced counting is attained and the number of bit transitions in the interlaced counting is made two at all times.This gray code counter is provided with: a gray code counter 2 in the configu...  
JP2006005703A
To solve the problem that an operation frequency does not go up because delay time varies between respective registers and the operation frequency is determined by a path having the maximum delay time when delay time of a combination log...  
JP2005348129A
To generate frequency dividing clocks of an inputted clock with high accuracy with the small number of elements without lowering operation frequency even when a clock with deteriorated duty cycle is inputted.Flip-flops 10-1 to 10-4 with ...  
JP2005341596A
To provide a frequency dividing circuit wherein processing frequency is high, and the occupied physical region and power consumption are small.A programmable frequency-dividing circuit with symmetrical output is disclosed. The frequency ...  
JP2005537601A
An electronic device (100) has a data storage device (120) which memorizes N data elements, and a data storage device (120) is equipped with the 1st set (122) of a data storage element (130). The 1st set (122) of a data storage element (...  
JP2005333567A
To provide a trigger signal generating circuit which is operable at high speed for generating a frequency-divided clock having a duty ratio of 50%.1st to Pth (P is an integer) sub-counters (SC1-SCP) provided in parallel and capable of co...  
JP2005333652A
To provide a technology relating to state correction for error correction.In a state circuit, a first flip-flop is connected to a second flip-flop. A state correction circuit is connected to the output of the second flip-flop. A third fl...  
JP2005311933A
To keep continuity of a count value when switching a count mode in an asynchronous counter circuit which is capable of switching the count mode.3-input and 1-output type three values switching parts 420 (422, 424, 426) for switching thre...  

Matches 801 - 850 out of 6,226