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Matches 851 - 900 out of 6,225

Document Document Title
JP2005303884A
To provide a flip-flop circuit in which power consumption can be reduced and a malfunction can be suppressed.In a flip-flop circuit comprised of a data input/output section 10, a clock input section 11 and a current supply section 12, bi...  
JP2005302278A
To prevent gradual degradation in the level of a signal to be inputted from each stage of a shift register to the next stage.A first stage RS1 (1) comprises five n-MOSs 201, 202, 203, 205 and 206. When the level of a signal Φ1 becomes a...  
JP2005293817A
To provide a shift register capable of preventing the fluctuation of the voltage of a node for controlling an output buffer part caused by the parasitic capacitor of a thin-film transistor, and its driving method.This shift register is p...  
JP3729032B2
To provide a data line side drive which surely operates even if an inhibit signal has a low driving ability. The data line side drive circuit 150A is provided with an X-shift register 151 in which each of shift register unit circuits Ua0...  
JP2005286797A
To provide a signal generating circuit capable of realizing the circuit layout independently of timing of produced pulses.A shift register 10 has a plurality of stages of registers 11 to 1n, and transmits a start pulse SP generated by a ...  
JP2005277875A
To provide a pulse swallow type variable divider which is faster than before even using the same manufacturing technology with conventional one, with no use of a device of fast operation and a device of high power.The divider comprises a...  
JP2005277665A
To shorten the lockup time by reducing reference spurious radiation of a PLL synthesizer.The frequency of a signal inputted to a main counter 12 and a swallow counter 11 is halved by inserting a half fixed frequency divider 10 to the pos...  
JP2005244956A
To improve both of rising characteristics and falling characteristics of an output signal in a flip-flop, and to reduce the signal delay of a shift register constituted by this flip-flop.A latch unit 22 has a latch circuit for latching a...  
JP3714875B2
To provide a gray code counter, with which skip counting is enabled and the number of bit transitions in skip counting is two at all the time. This gray code counter is provided with a gray code counter 2 in the configuration of 5 bits f...  
JP3711455B2
To provide a high-speed multi-bit binary counter circuit. In a multi-bit counter circuit in which 1-bit counter circuits 1 are coupled in series, the 1-bit counter circuits 1 are separated into at least one lower order 1-bit counter 1 ta...  
JP2005223829A
To provide a fractional frequency divider circuit which reduces its circuit scale and outputs a clock of a duty ratio 50%, and data transmission apparatus having the frequency divider circuit.A fractional frequency divider circuit includ...  
JP3707203B2
To provide a frequency divider where a clock signal is frequency- divided at frequency division ratios including a half cycle of the clock signal. The frequency divider is made up of a 1/(2n+1) frequency divider 1, a duty adjustment devi...  
JP3703347B2
To provide a frequency divider circuit from which a frequency division ratio of 2 over odd numbers with a simple circuit configuration. The frequency divider circuit comprises a flip-flop multi-stage circuit G consisting of n-sets of fli...  
JP2005198296A
To provide a numeric counter oscillator (NCO) of high-level accuracy for making a frequency resolution more flexible.An NCO has a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for rec...  
JP2005198339A
To provide a programmable frequency divider for a phase lock loop having a latch circuit with a first input receiving a program integer and an output deriving a latch integer.A phase lock loop monitors a first digital signal and derives ...  
JP2005198164A
To provide a PLL synthesizer for adopting a fractional frequency division system employing a delta sigma circuit for realizing a low consumed current without deteriorating the characteristic.A period shared by "H" levels is equal to a pe...  
JP3696004B2
To provide a semiconductor circuit wherein respective outputs of cascaded flip-flops never reach unintended values. This semiconductor circuit is constituted by cascading (n) register circuits REG0 to REGn-1. Each register circuit select...  
JP3696899B2
PURPOSE: To lead out lock detection signals by providing first input for receiving a program integer and a latch circuit for leading out a latch integer. CONSTITUTION: A phase detector 14 generates UP or DOWN signals by the phase relatio...  
JP3688683B2
To generate a precise fraction frequency division signal irrespective of precision of a decimal part of a frequency-divided number. A cumulative adder 7 performs cumulative addition of a decimal value f set in an f setting part 8 in resp...  
JP2005159737A
To speed up operating speed in a frequency dividing circuit in a variable frequency dividing circuit effective to a circuit that has a number of dividing stages and requires high-speed operation.There are provided a shift register compos...  
JP2005151284A
To stably obtain frequency dividing ratios 4, 8, 12, ..., 4N in a configuration of a small circuit scale and low power consumption.Two stages of the same elements each composed of an inverter circuit 21, a capacitor 41 and a switch circu...  
JP3682765B2
To provide a frequency divider that is operated at a high speed. The frequency divider comprises a latch circuit L101, an inverting circuit IV102, and an IV105 that is in a closed loop connection. The latch circuit L101 consists of a tra...  
JP2005141885A
To provide an address control circuit which is reduced in circuit size and can perform high-speed operation.The device is equipped with a first counter 11a and a second counter 11b. Based on a switching signal SS for switching whether an...  
JP3666078B2
To provide a circuit by which plural frequencies can be obtained and which can be used for the speed control of a pulse motor and the like by inverting the logic value of an output signal when a frequency division counter value is matche...  
JP3666352B2
To solve a problems that a malfunction takes place because a clock cycle becomes so short that internal delay can not follow when noise is mixed with a clock in the conventional frequency dividing circuit and that only noise below fixed ...  
JP2005510109A
A programmable divider supplies a low-speed changes signal more, in order to attain the synchronous load of the new divisor value of the midst of the safe load period of a programmable divider so that division may take place only using a...  
JP2005094753A
To provide a programmable low-power high-frequency divider circuit.A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter stag...  
JP2005508577A
Equipment (70) for forming the output signal (fdiv) in which the frequency is lower than the frequency of an input signal (CK1). Equipment (70) is equipped with the chain which consists of a frequency division cell (from 71 to 76), and e...  
JP2005508108A
It is equipment (50) for generating the output signal (fdiv) which has frequency lower than the frequency of an input signal (CK1, fvco). Have equipment (50) and the chain of a dividing cell (51 to 56) each of a dividing cell (51 to 56),...  
JP3657191B2
To provide an up/down gray code counter whose circuit scale can be made small. This up/down gray code counter is provided with an up count gray code counter 3 for performing only up counting and a most significant bit data selecting mean...  
JP3654153B2
To provide a clock signal generator that can reduce power consumed by its circuit sections not substantially requiring operations. A frequency divider side selection output means 35 stops the operation of a frequency divider circuit 24 a...  
JP2005064995A
To suppress jitter occurring internally without increasing power consumption.A synchronization compensation circuit 1-2 is provided on the poststage of a frequency divider 1-1. A master clock is inputted to a branch of the synchronizatio...  
JP2005057463A
To provide a two-modulus prescaler circuit which operates with low power consumption.In the prescaler circuit, each of 1st to (n-2)th D flip-flops is equipped with a 1st latch circuit having a couple of MOS switches, a 1st differential p...  
JP3649874B2
To provide a frequency divider which performs the division of frequency that is not equal to an integral multiple of an input signal. This divider 10 can perform both 1/X division and 1/(X+1) division (X: an integer). The frequency of an...  
JP3649640B2
To provide a semiconductor resistor element where power consumption in a CMOS semiconductor integrated circuit can be reduced in stands by. When a system shifts to standing by, the application of an input voltage to a temporary storage e...  
JPWO2005018094A
Transistor switch SWA which attaches and detaches electrically between an output of flip-flop FF64 of shift register SR1, and inputs of flip-flop FF65 of shift register SR2 in semiconductor integrated circuit device 1, It has transistor ...  
JP2005505979A
Some 1: 2 asynchronous dividers to which the present invention was connected in series (10, 12), It is related with 2 Mohd dividing counting circuit equipped with phase selector Brock (11) inserted between two dividers [1: 2] (10, 12), a...  
JP2005045507A
To provide a non-integer frequency divider that can be constituted by combining the circuits with simple functions and whose frequency division ratio can simply be set.This non-integer frequency divider has an adder 11 which adds a 1st s...  
JP2005037169A
To provide a semiconductor integrated circuit allowing knowledge of power consumption of each functional block.This semiconductor integrated circuit has: first to third signal processing circuits 11-13 respectively operating in synchroni...  
JP3618301B2  
JP2005025151A
To provide a bidirectional shift register capable of judging whether the register operates normally in any bidirection without increasing inspection terminals, and a display device equipped with the bidirectional shift register.The bidir...  
JP2005502256A
A clock separator circuit contains the state machine which receives an input clock signal and generates an exclusive set control signal and reset control signal mutually. A set pass gate and a reset pass gate are controlled using a set c...  
JP3612886B2  
JP2005012515A
To provide a variable frequency divider by eliminating a path with a greater capacity load such as a critical path and to achieve low power consumption.A feedback path 207 is formed between an output of a fixed frequency divider 205 and ...  
JP3633299B2
To take out a tripartite output signal of a duty factor 50% from an inputted signal. A signal inputted from outside and another signal are inputted to a multiplier circuit 2, and a signal taken out from it is inputted to an amplifier 3 t...  
JP3631573B2
To digitally reduce an electromagnetic interference noise level by obtaining a first signal from a base signal by means of a digital system so as to execute modulation, obtaining a modulation reference signal which is fluctuated between ...  
JP2004363821A
To provide a frequency-dividing circuit that can obtain various numbers of frequency division with the same constitution and perform stable frequency division even when an input reference clock is fast.The frequency-dividing circuit is e...  
JP3631375B2
To provide a frequency divider capable of enlarging a frequency range and performing a high-speed operation by changing a free-run frequency without largely changing an output signal amplitude. This frequency divider is composed of two b...  
JP2004364105A
To improve the maximum operation frequency of a prescaler circuit 1 without depending on the process of an element.Flip-flops FF1 to FF3 apply 1/4-frequency division to a clock inputted to a clock terminal by feedbacking the output of th...  
JP3629050B2
PURPOSE: To increase the operation speed by transmitting a carry signal by combination of gate means. CONSTITUTION: A carry signal CAR1 is transmitted through two stages of gate delay where a signal CAR0 passes a NAND gates 51 through a ...  

Matches 851 - 900 out of 6,225