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Matches 901 - 950 out of 6,231

Document Document Title
JP3618918B2
To reduce a signal amount on the whole by decreasing the number of input signals. As for an A, a B, and a C signal of '1' and '0' outputted from an input circuit 1, a state change decision circuit 3 decides whether or not the B and C sig...  
JP2005025151A
To provide a bidirectional shift register capable of judging whether the register operates normally in any bidirection without increasing inspection terminals, and a display device equipped with the bidirectional shift register.The bidir...  
JP2005502256A
A clock separator circuit contains the state machine which receives an input clock signal and generates an exclusive set control signal and reset control signal mutually. A set pass gate and a reset pass gate are controlled using a set c...  
JP3612886B2  
JP2005012515A
To provide a variable frequency divider by eliminating a path with a greater capacity load such as a critical path and to achieve low power consumption.A feedback path 207 is formed between an output of a fixed frequency divider 205 and ...  
JP3609601B2
To easily confirm whether timer counter operation is normal or abnormal by incorporating a function for detecting the counter operation being abnormal according to the result of logical operation between the time of the timer counter cir...  
JP2004363821A
To provide a frequency-dividing circuit that can obtain various numbers of frequency division with the same constitution and perform stable frequency division even when an input reference clock is fast.The frequency-dividing circuit is e...  
JP2004364105A
To improve the maximum operation frequency of a prescaler circuit 1 without depending on the process of an element.Flip-flops FF1 to FF3 apply 1/4-frequency division to a clock inputted to a clock terminal by feedbacking the output of th...  
JP3601961B2  
JP2004537188A
The system and method for generating a polyphase clock are indicated. In 1 enforcement form, the multi-stage voltage controlled oscillator ("VCO") (302) transmits two or more clock phases (ck*ck) to the clock divider (304) which generate...  
JP2004342093A
To generate multiple clock signals so as to establish distinct phase relations between clock signals having different frequencies.A device adapted to supply a plurality of clock signals is obtained. The device is provided with a pair of ...  
JPWO2004105247A
A feeding back pass (307) is formed between the output (310c) of a fixed counting-down circuit (305), and the control terminal (310b) of reversal / reversed vessel (304). A connector (306) is provided in a feeding back pass (307), a feed...  
JP2004335094A
To solve the problem wherein it is not possible to read/write at high speed, because the conventional DRAM latches the line address and the column address by DFF and the address decoding is conducted a fixed time later, after the clock s...  
JP2004336232A
To generate a frequency divided clock usable for the reference clock, even when the ratio of an oscillation frequency to a divided frequency is not an integer one.The frequency division circuit comprises a crystal oscillator circuit 1 fo...  
JP2004328301A
To provide a variable frequency divider capable of performing a more stable high-speed operation without increasing the bit width of a counter.N1 is loaded as an initial value on a binary down-counter 12 when a count value becomes -N2. A...  
JP2004328300A
To provide a variable frequency divider capable of performing a stable high-speed operation.A prescaler 10 switches a frequency dividing ratio according to a level of a frequency dividing ratio control signal PCTR outputted from a swallo...  
JP2004320515A
To provide two poles analog monitor voltage generating circuit in which positive/negative voltages can be outputted from an output of ASIC with a single power source.In a digital/analog converter, a D-flip flop 2 holds data when BRM1 out...  
JP2004289422A
To reduce the power consumption and a required number of FF circuits.The frequency divider circuit is provided with: a high speed frequency divider circuit 11 comprising a high speed operating device, applying 1/M frequency division to a...  
JP2004531107A
A lock detect signal generator with the present efficient invention, VCO of the extended range which can operate within the limits of one with an adjoining arbitrary characteristic curve of the plurality specified by two or more adjoinin...  
JP3572908B2  
JP3571228B2  
JP3567309B2  
JP3567820B2  
JP3566342B2
PURPOSE: To provide a parallelly operated high-speed counter for making high- speed counting possible by parallelly operating the two counters of two system for the high-speed counting impossible by one counter. CONSTITUTION: This counte...  
JP3563198B2
To control counting of an up-down counter circuit with two input terminals. When input signals given to two input terminals 1, 2 both set to a low level, a value of the counter is reset to '0'. When an input signal of either of the two i...  
JP3563265B2
To attain miniaturization and low power consumption by constructing a frequency divider with a small number of transistors. A current is fed by a current source which consists of transistors D1 to D4, whose gates and sources are connecte...  
JP3561657B2  
JP2004236193A
To generate a precise fraction frequency division signal irrespective of precision of a decimal part of a frequency-divided number.A cumulative adder 7 performs cumulative addition of a decimal value f set in an f setting part 8 in respo...  
JP3553753B2
To enable a PLL circuit to reduce a frequency of an operation clock that detects a pulse. A pulse detecting part 10 samples a pulse signal to be demodulated, based on an operation clock. An operation clock generating part 9 generates an ...  
JP2004222212A
To provide a counter circuit whose scale is prevented from being made large by reducing the number of gates, chip areas.The counter circuit is provided with a half adder 11, registers 12-P, 12-Q, 12-R, 12-S and a multiplexer 13-2. The ha...  
JP3548925B2  
JP2004214909A
To provide a frequency dividing circuit which is capable of dividing input clocks of high frequency to obtain a sub-harmonic output and operating stably at a high frequency.Resistors R5 to R8 are arranged between two differential amplifi...  
JP2004201169A
To accelerate an operating speed of a PLL circuit using a 4-to-1 multiplexer and to reduce power consumption thereof.The 4-to-1 multiplexer 1 for selecting one signal from among signals whose phases are 0°, 90°, 180° and 270° formed ...  
JPWO2004057760A
The present invention makes the input part of an inverter the threshold potential of an inverter, and it is inputting CK signal into the input part of an inverter via a capacity means, and CK signal is amplified, and uses the amplified C...  
JP2004519917A
A frequency synthesizer (200) permits half cycle dividing of the compounded frequency. In the conventional sigma*delta N dividing frequency synthesizer, a controllable divider permits dividing of the frequency compounded by the integer f...  
JP2004519958A
The fraction frequency divider in which a program is possible makes finer dividing ability more possible than the conventional integer frequency divider to output frequency. The fraction frequency divider in which the program of the pres...  
JP2004165757A
To provide a device capable of suppressing a clock frequency to low because a circuit operates at the frequency of an input clock, and reducing the power consumption of the circuit and heat generation associated therewith.The circuit for...  
JP2004517542A
A digital frequency multiplier carries out nonintegral double [of the frequency of an input signal]. A multiplexer receives an input signal and the signal which has the frequency of the integral multiple of this input signal. /by a multi...  
JP3536073B2
PURPOSE: To obtain the frequency divider with decimal fraction in which switchover and setting of a frequency division ratio are conducted at a high speed in order to reduce phase noise of a frequency synthesizer so as to increase a resp...  
JP2004516768A
A プリスケーラ Boolean part, a エンドオブ cycle Boolean part, and the clock input unit for receiving the input clock of the frequency fn, the output clock part for supplying the output clock of the frequency fm to the followin...  
JP3522584B2
To surely and stably release a power saving state by providing a step for generating a first initialization signal for initializing a reference signal frequency dividing step and a step for generating a second initialization signal for i...  
JP2004128767A
To provide a flip-flop circuit capable of deciding an initial logic value in an ECL circuit.The flip-flop circuit 2 is provided with ECL circuits 11 to 14 each comprising transistor pairs whose emitters are connected. The flip-flop circu...  
JP3519346B2
To obtain a low whole frequency division ratio by means of a high frequency division ration in a preceding frequency dividing period and the low frequency division ratio of a main frequency divider by providing a plurality of different f...  
JP2004110902A
To provide a counting circuit which permits easy changing of conditions of detected signals and is simple and small in configuration and a nonvolatile semiconductor memory which uses the same.The pulse counting circuit which counts the p...  
JP3516590B2
To obtain a frequency divider that receives a very high frequency signal by dynamically selecting a couple of division ratios from among division ratio pairs as a function for a selection signal for the prescaler and configuring an opera...  
JP3514532B2
PURPOSE: To minimize the deviation of an actual output frequency from a desired output frequency for the same input clock and to improve the accuracy of output clocks. CONSTITUTION: This generator is provided with a timer part 1 for gene...  
JP3510903B2
PURPOSE: To provide a high-speed adder (provided with a subtractor) and a counter constituted of a programmable lookup table in a programmable logic device. CONSTITUTION: A conventional lookup table 10 is divided into smaller lookup tabl...  
JP2004509499A
The counter for compounding a clock signal by the minimum jitter. The selection circuitry for the counter of the present invention to choose the output of the output of the counter stage of the above 1st or the above-mentioned look ahead...  
JP3508762B2
To provide a frequency divider circuit in which the delay time of a clock signal is hardly changed even when the frequency dividing ratio of the inputted clock signal is changed. The frequency divider circuit has a frequency dividing mea...  
JP2004507824A
the gray code used for FIFO of a RAM base -- calculation -- system AP1 is equipped with the read pointer 10, the writing pointer 20, and the detector 30. A read pointer -- the gray code decoder 11, the binary incrementor 12, the gray cod...  

Matches 901 - 950 out of 6,231