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WO/2013/140755A1 |
An injection-locked frequency divider (ILFD) control unit (520) establishes a control parameter of an IFLD (303b) on the basis of the frequencies of a reference signal and of a frequency-divided signal measured in accordance with a contr...
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WO/2013/121149A1 |
According to this method, a carry generation command (M) is applied repetitively to a command input (G) of a carry-propagation logic circuit (1), the application of said command (M) to said input (G) is timed by means of a reference cloc...
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WO/2013/098127A1 |
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-...
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WO/2013/073268A1 |
A latch circuit (1) is equipped with: a PMOS transistor (10), the drain of which is connected to a first output node and the gate of which is connected to a second output node; a PMOS transistor (12), the drain of which is connected to t...
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WO/2013/062855A1 |
A mixed-signal radio frequency receiver implements multiple spur avoidance modes to reduce or remove spurs or digital noise injection into the received channel to enhance the receiver performance. The multiple spur avoidance modes are re...
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WO/2013/057060A1 |
A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an ...
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WO/2013/048525A1 |
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division...
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WO/2013/020900A1 |
A frequency divider (100) comprises a signal generation stage (110) arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first...
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WO/2013/012755A1 |
Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multip...
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WO/2013/009918A1 |
A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching betwee...
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WO/2013/000849A2 |
The invention relates to an electronic circuit especially comprising: a comparator (12) receiving a threshold potential (Vcomp) and the potential of an integration node (N), said node being able to store electrical charges generated by a...
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WO/2012/167686A1 |
Disclosed are a frequency division device and method. The device includes: a feedback control platform, a multiplexing frequency divider; the feedback control platform including a parameter setting module being set to set an initial valu...
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WO/2012/168533A1 |
An apparatus comprising a clock shaper (510) configured to derive a frequency of a reference clock signal (501) into a plurality of n frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1,..., Clock n-1 (571-0, 571-1,...
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WO/2012/161003A1 |
A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number o...
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WO/2012/150621A1 |
A frequency synthesizer according to the present invention is provided with a decimal part data output unit (10) which generates two values for decimal part data (F, F+1) and outputs either one of the generated two values by switching ba...
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WO/2012/131795A1 |
A CML clock division circuit (1A) according to the present invention is provided with a plurality of latch circuits (31, 32) having a first and a second transistor groups (301, 302) which receive clock signals (CLK1, NCLK1) at the gates ...
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WO/2012/129553A1 |
A frequency divider circuit is described. The frequency divider circuit (602) includes a first cross - coupling (606a). The first cross - coupling (606a) includes a first cross - coupled transistor (650a) with a first gate (608a). The fi...
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WO/2012/103090A1 |
A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly div...
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WO/2012/035941A1 |
The disclosed frequency divider circuit is provided with: a variable frequency divider (2) which frequency-divides a periodic signal (s5) with two frequency division ratios and outputs a first frequency-divided signal (c1); a counter cir...
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WO/2012/035800A1 |
A frequency division circuit according to the present invention comprises: a variable-frequency divider (2) that outputs a first frequency-divided signal (c1) obtained by frequency division of a periodic signal (s5) at two different freq...
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WO/2012/021511A2 |
A frequency divider (200) includes a least significant (LS) stage (220), multiple cascaded divider stages (230-1 to 230-N), and an output stage (210). The LS stage (220) receives an input signal (201), a program bit and a first mode sign...
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WO/2012/014060A1 |
A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input...
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WO/2011/156622A1 |
Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase base...
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WO/2011/125566A1 |
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal outpu...
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WO/2011/108343A1 |
An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor ...
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WO/2011/103103A1 |
A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circ...
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WO/2011/079630A1 |
The present invention discloses a method for clock frequency division, the method includes: determining current frequency division coefficient in real time according to input clock signals and output clock information; then, performing c...
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WO/2011/063749A1 |
The present invention discloses a method for generating a low-jitter clock, which comprises the following steps: interpolating time delay in each low-speed clock period to finely adjust a high-speed clock; and then performing frequency d...
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WO/2011/053634A1 |
Techniques for synthesizing a signal having a desired frequency from an oscillation signal. In an aspect, a reference signal having a known frequency may be periodically used to determine a ratio between the desired frequency and the fre...
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WO/2011/047861A1 |
Ring oscillator comprising a plurality of elementary units (5) connected in cascade and linked in order to make a chain with the respective output terminals (OUT) connected to the input terminals (IN) of the successive elementary units (...
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WO/2011/046015A1 |
To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and ...
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WO/2011/028157A1 |
The invention relates to a high-speed non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices each having an input terminal, a clock terminal a...
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WO/2011/023030A1 |
An integrated circuit is disclosed in present invention, which includes: a first frequency division unit, a counter, an oscillation signal generation circuit and a second frequency division unit; wherein: the first frequency division uni...
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WO/2011/008999A1 |
A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clock...
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WO/2010/146756A1 |
Disclosed is a flip-flop provided with a first CMOS circuit in which the gate terminals and drain terminals of a P channel first transistor and an N channel second transistor are connected, a second CMOS circuit in which the gate termina...
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WO/2010/134257A1 |
Disclosed is a CMOS inverter type frequency divider with further reduced power consumption compared with the past. The CMOS inverter type frequency divider is provided with a plurality of CMOS inverters, a frequency division control unit...
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WO/2010/108037A1 |
A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a ...
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WO/2010/070830A1 |
A clock frequency divider circuit for generating a clock signal that allows an expected correct communication operation to be performed in communication with a circuit that operates on a clock having a different frequency. The clock fre...
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WO/2010/061814A1 |
Provided is a counter circuit having a simple circuit configuration which can switch the delay time from one to another. The counter circuit includes flip-flops of a plurality of stages which are longitudinally connected. A clock from a...
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WO/2010/052215A2 |
According to an embodiment of a time to digital converter, the time difference between a signal of interest and a reference signal is measured by operating a digitally controlled oscillator at a first frequency during a first portion of ...
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WO/2010/050097A1 |
Provided is a clock division circuit which generates a clock signal enabling execution or a correct communication expected in the communication with a circuit operating at a different frequency clock. The clock division circuits (10a, b...
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WO/2010/050098A1 |
A clock division circuit (11) masks (S – N) clock pulses among S clock pulses of an input clock signal according to a division ratio defined by an N/S and generates an output clock signal obtained by N/S-dividing the input clock signal...
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WO/2010/033855A2 |
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (...
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WO/2010/022092A1 |
A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q...
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WO/2010/022366A1 |
In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse ...
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WO/2010/004747A1 |
Provided is a divider circuit for a multi-phase clock signal which can assure a sufficient data latch time even for a multi-phase clock signal having a high frequency. For example, the divider circuit includes: a main latch circuit (10)...
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WO/2010/004508A1 |
A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (A...
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WO/2009/133380A2 |
A fractional-n frequency divider that overcomes the presence of so-called dead zones in known frequency divider circuits, n divider cells (3) are connected so as to form a ripple counter (n being an integer greater than or equal to two) ...
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WO/2009/125580A1 |
Provided is a loop type clock adjustment circuit including: a variable delay circuit which applies a variable delay based on an analog signal to a reference clock so as to generate a delay clock; a phase detection unit which detects a ph...
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WO/2009/116398A1 |
A clock signal division circuit includes a mask circuit (10) and a mask control circuit (20). The mask circuit (10) masks a clock pulse of a clock S in accordance with an inputted mask signal (50) so as to generate a clock B for output. ...
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