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Matches 51 - 100 out of 6,211

Document Document Title
WO/2012/021511A2
A frequency divider (200) includes a least significant (LS) stage (220), multiple cascaded divider stages (230-1 to 230-N), and an output stage (210). The LS stage (220) receives an input signal (201), a program bit and a first mode sign...  
WO/2012/014060A1
A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input...  
WO/2011/156622A1
Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase base...  
WO/2011/125566A1
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal outpu...  
WO/2011/108343A1
An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor ...  
WO/2011/103103A1
A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circ...  
WO/2011/079630A1
The present invention discloses a method for clock frequency division, the method includes: determining current frequency division coefficient in real time according to input clock signals and output clock information; then, performing c...  
WO/2011/063749A1
The present invention discloses a method for generating a low-jitter clock, which comprises the following steps: interpolating time delay in each low-speed clock period to finely adjust a high-speed clock; and then performing frequency d...  
WO/2011/053634A1
Techniques for synthesizing a signal having a desired frequency from an oscillation signal. In an aspect, a reference signal having a known frequency may be periodically used to determine a ratio between the desired frequency and the fre...  
WO/2011/047861A1
Ring oscillator comprising a plurality of elementary units (5) connected in cascade and linked in order to make a chain with the respective output terminals (OUT) connected to the input terminals (IN) of the successive elementary units (...  
WO/2011/046015A1
To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and ...  
WO/2011/028157A1
The invention relates to a high-speed non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices each having an input terminal, a clock terminal a...  
WO/2011/023030A1
An integrated circuit is disclosed in present invention, which includes: a first frequency division unit, a counter, an oscillation signal generation circuit and a second frequency division unit; wherein: the first frequency division uni...  
WO/2011/008999A1
A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clock...  
WO/2010/151891A3
Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a seco...  
WO/2010/146756A1
Disclosed is a flip-flop provided with a first CMOS circuit in which the gate terminals and drain terminals of a P channel first transistor and an N channel second transistor are connected, a second CMOS circuit in which the gate termina...  
WO/2010/134257A1
Disclosed is a CMOS inverter type frequency divider with further reduced power consumption compared with the past. The CMOS inverter type frequency divider is provided with a plurality of CMOS inverters, a frequency division control unit...  
WO/2010/033855A3
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (...  
WO/2010/108037A1
A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a ...  
WO/2010/070830A1
A clock frequency divider circuit for generating a clock signal that allows an expected correct communication operation to be performed in communication with a circuit that operates on a clock having a different frequency. The clock fre...  
WO/2010/061814A1
Provided is a counter circuit having a simple circuit configuration which can switch the delay time from one to another. The counter circuit includes flip-flops of a plurality of stages which are longitudinally connected. A clock from a...  
WO/2010/052215A2
According to an embodiment of a time to digital converter, the time difference between a signal of interest and a reference signal is measured by operating a digitally controlled oscillator at a first frequency during a first portion of ...  
WO/2010/050097A1
Provided is a clock division circuit which generates a clock signal enabling execution or a correct communication expected in the communication with a circuit operating at a different frequency clock. The clock division circuits (10a, b...  
WO/2010/050098A1
A clock division circuit (11) masks (S – N) clock pulses among S clock pulses of an input clock signal according to a division ratio defined by an N/S and generates an output clock signal obtained by N/S-dividing the input clock signal...  
WO/2010/033855A2
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (...  
WO/2010/022092A1
A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q...  
WO/2010/022366A8
In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse ...  
WO/2010/022366A1
In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse ...  
WO/2010/004747A1
Provided is a divider circuit for a multi-phase clock signal which can assure a sufficient data latch time even for a multi-phase clock signal having a high frequency. For example, the divider circuit includes: a main latch circuit (10)...  
WO/2010/004508A1
A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (A...  
WO/2009/133380A3
A fractional-n frequency divider that overcomes the presence of so-called dead zones in known frequency divider circuits, n divider cells (3) are connected so as to form a ripple counter (n being an integer greater than or equal to two) ...  
WO/2009/133380A2
A fractional-n frequency divider that overcomes the presence of so-called dead zones in known frequency divider circuits, n divider cells (3) are connected so as to form a ripple counter (n being an integer greater than or equal to two) ...  
WO/2009/125580A1
Provided is a loop type clock adjustment circuit including: a variable delay circuit which applies a variable delay based on an analog signal to a reference clock so as to generate a delay clock; a phase detection unit which detects a ph...  
WO/2009/116398A1
A clock signal division circuit includes a mask circuit (10) and a mask control circuit (20). The mask circuit (10) masks a clock pulse of a clock S in accordance with an inputted mask signal (50) so as to generate a clock B for output. ...  
WO/2009/116399A1
A clock signal division circuit includes a mask circuit (10B) and a mask control circuit (20B). The mask circuit (10B) masks a clock pulse of a clock S in accordance with an inputted mask signal (50B) so as to generate a clock B. The mas...  
WO/2009/107105A3
In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount...  
WO/2009/107105A2
In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount...  
WO/2009/095279A1
A local oscillator circuit for a signal transmitter or receiver, the circuit comprising: an input for receiving a master oscillating signal from a master oscillator; and signal processing circuitry configured to be clocked by the master ...  
WO/2009/089410A3
In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output ...  
WO/2009/050854A1
There is provided a circuit comprising a logic circuit and a current amplification circuit. The logic circuit has a first transistor disposed on the high side of a power supply and a second transistor disposed on the low side of the powe...  
WO/2009/050039A2
A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2,...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an...  
WO/2009/050039A3
A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2,...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an...  
WO/2009/041474A1
An A/D converting circuit, a solid-state image sensing device and a camera system in which a counter is capable of counting on both edges of a clock as well as being switchable while keeping an up/down count, and which prevents deteriora...  
WO/2009/021251A1
The invention relates to a method and a device for decreasing the frequency of a digital clock signal (A). According to the invention, the clock pulses of the digital clock signal (A) are linked with a control signal (B), which is synchr...  
WO/2009/021251A9
The invention relates to a method and a device for decreasing the frequency of a digital clock signal (A). According to the invention, the clock pulses of the digital clock signal (A) are linked with a control signal (B), which is synchr...  
WO/2008/122958A3
The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting...  
WO/2008/122958A2
The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting...  
WO/2008/120150A2
A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge t...  
WO/2008/120150A3
A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge t...  
WO/2008/113105A1
A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received and a clock control circuit to receive the clock ...  

Matches 51 - 100 out of 6,211