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Document Title |
JPH0922591A |
To improve an access speed to a sequential data block. A counter circuit 10 generates selectively count sequence in a binary count mode and an interleave count mode. A counter 16 is composed of three T flip-flops. A toggle control signal...
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JPH0923159A |
To reduce the power consumption of a time counting device using a high speed reference clock. When time counting is not executed in a time counting device for counting gate time by countting up a reference clock CLK(CLKG) generated from ...
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JPH0923152A |
To mechanically increase the number of counts by time-dividedly transferring counter data of prescribed timing from a memory storing counter data of all timing. When a clock CLK3 generated by a clock generating circuit is applied to an o...
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JP2572448B2 |
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JP2571622B2 |
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JP2572302B2 |
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JP2572283B2 |
A programmable frequency divider for dividing the frequency of a supplied high-frequency signal directly into a lower frequency includes a plurality of 2-scale-factor prescalers or programmable frequency divider units each capable of bei...
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JPH098650A |
PURPOSE: To provide a device for counting production of a specific input between plural consecutive periods. CONSTITUTION: This device includes an input terminal to receive an input signal, a toggle signal generating circuit (12) to gene...
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JP2569589B2 |
Disclosed is a combination of a counter operating in response to an input signal, a latch circuit for latching the output of the counter and a read-command signal inhibiting circuit controlling the latch circuit so as not to effect the l...
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JP2567166B2 |
PURPOSE: To simplify the circuit and to decrease the cost by providing a frequency dividing means, two up counters, a clock generating means, a counter controlling means and two coincidence detecting means. CONSTITUTION: A first up count...
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JP2567163B2 |
PURPOSE: To obtain an original oscillating output with less noise or without noise generated from a frequency divider circuit by stopping the frequency divider circuit when the original oscillation output is extracted from an oscillation...
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JPH08339685A |
To improve the speed of response of the output signal of a high-speed counter circuit to inputted clock signals by operating a highest-order bit counter and a lowest-order bit counter synchronously to the clock signals. First to sixth bi...
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JP2565592B2 |
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JP2564812B2 |
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JP2565248B2 |
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JP2564915B2 |
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JPH08335859A |
PURPOSE: To realize a technique which eliminates the skew error between a non-divided signal and a 2-divided signal of a variable 2 frequency dividing circuit. CONSTITUTION: A variable 2 frequency dividing circuit 100 provided with a D t...
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JPH08330946A |
PURPOSE: To provide a time count circuit which can measure the pulse intervals of pulse signals with high accuracy and small power consumption. CONSTITUTION: This time count circuit is provided with an inverter ring 11 which consists of ...
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JP2563460B2 |
A 1.2 mu m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to dete...
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JP2563238B2 |
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JP2563578B2 |
A high speed CMOS binary up/down counter (10) having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter (10) performs in an up-count mode or a down-count mode in accor...
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JPH08316825A |
To attain time measurement having an accuracy of (1-f) second order, when (f) is operation frequency in a high-speed counting system operating at a frequency >=about 800 MHz. The least significant bit(LSB) of a counter 12 is driven by th...
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JPH08316867A |
PURPOSE: To set a frequency division ratio of an asynchronous variable frequency divider circuit to an object value with a simple configuration. CONSTITUTION: The frequency divider circuit is provided with an asynchronous counter 31M com...
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JP2557954B2 |
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JP2558769B2 |
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JPH08307247A |
To provide an N+1 frequency dividing counter which has a 50% duty cycle against all count values N and can be applied when the N is zero without requiring an excessive circuit. An N+1 frequency dividing counter 20 is provided with a bina...
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JP2555978B2 |
PURPOSE: To provide an odd number frequency divider circuit simple in circuit configuration, easy to change a frequency division ratio and capable of obtaining the output of duty factor of 50%. CONSTITUTION: A master clock noninverting s...
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JP2553568B2 |
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JP2554064B2 |
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JPH08298455A |
PURPOSE: To prevent option key input errors through the use of a key protect function by processing the input in response to a valid/inhibit state corresponding to the key and the switching state of a protect switch. CONSTITUTION: The pr...
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JP2548784B2 |
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JP2547723B2 |
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JP2545986B2 |
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JPH08274627A |
PURPOSE: To prevent the miscounting so as to enable a user to set a proper counting speed in response to the count inputs to be actually counted by the user by setting the highest counting speed according to an input speed and counting t...
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JPH08272479A |
PURPOSE: To suppress increase of the current consumption of a power supply without deteriorating the overall system performance. CONSTITUTION: A variable clock generation device supplies the clocks to the units 31 and 32 which operate by...
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JP2543290B2 |
PURPOSE: To provide a frequency divider capable of highly accurately setting up frequency while holding high loop gain by the small number of frequency divider steps and accelerating a channel switching time for a synthesizer without inc...
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JP2544975B2 |
A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks an...
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JP2543108B2 |
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JPH08265138A |
PURPOSE: To use a count before the replacement of a battery or a counter succeedingly even after the replacement. CONSTITUTION: The counter is provided with a fast feed button 5 operated to feed a count of a counter at a high speed and a...
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JP2541398B2 |
PURPOSE: To deviate an operation frequency by providing a phase comparing means, a clocking means, a programmable dividing means, a digital means that generates a clock signal, an adjusting means which adds or subtracts and a dividing me...
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JP2538786B2 |
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JPH08256041A |
To eliminate propagation difference of different combination logic clocks of upstream and downstream state machines(SM). A trigger circuit 34 applies an output state to a downstream SM 12 in response to the appearance of an appropriate c...
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JPH08251028A |
To reduce an error and to make noise low by allowing a bit control circuit to adjust current output bits in response to a comparison signal by using a control value and compensating an error due to a through rate. A successive approximat...
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JP2536222B2 |
PURPOSE:To suppress self-oscillation specific to a frequency dividing circuit while the difference of an input DC offset current is minimized by selecting the size of the emitter of a transistor(TR) through which a current for a slave am...
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JP2535921B2 |
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JPH08237112A |
PURPOSE: To divide a counter circuit into plural counters of an optional bit length by allowing a register group to designate enable/inhibit a carry output A/a level of power supply and count operation of a unit counter group outputting ...
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JP2533492B2 |
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JP2533758B2 |
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JP2530663B2 |
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JPH08223028A |
PURPOSE: To reduce the scale and the power consumption of an apparatus and to improve the reliability of a binary counter by securing the same connection among the JK flip-flops and the logical combination circuits and controllings optio...
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