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Matches 101 - 150 out of 6,228

Document Document Title
WO/2008/122958A3
The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting...  
WO/2008/120150A3
A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge t...  
WO/2008/122958A2
The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting...  
WO/2008/120150A2
A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge t...  
WO/2008/113105A1
A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received and a clock control circuit to receive the clock ...  
WO/2008/078617A1
Provided is a high-speed programmable synchronous counter, which realizes a programmable synchronous counter having a long word tone in a high-frequency band without using a dedicated IC, while warranting a high timing precision. The hig...  
WO/2008/065869A1
[PROBLEMS] To provide a rational number frequency dividing circuit wherein the variations in cycle times of frequency-divided clock signals are small, there are many occasions in which the minimum cycle time of frequency-divided clock si...  
WO/2008/014282A3
A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and output...  
WO/2008/056551A1
A rational number frequency divider circuit wherein the cycle time of a frequency-divided clock signal is constant and wherein the power consumption, layout area and design/test costs are small. A clock signal frequency divider circuit, ...  
WO/2008/044023A1
A spread-period clock generator (SPC) counts basic clock pulses (XK) to generate output pulses (EQ) with varying periods, and has means (controlled by signal QS) for switching between a first mode, in which counting is carried out in res...  
WO/2008/033979A2
Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter include...  
WO/2008/014594A1
An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The c...  
WO/2008/002968A1
A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also rece...  
WO/2007/135793A1
In a counter circuit (1) of a control signal generation circuit (2), a selection circuit (3) selects a predetermined signal from an HSYNC signal and a VSYNC signal as a pulse signal and inputs the same to a counter (4) in accordance with...  
WO/2007/004182A3
A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one la...  
WO/2006/047622A3
A signal converter is comprised of a plurality of counters ("macro-counters"). In turn, each of the macro-counters is comprised of a plurality of single-bit counters ("micro-counters") that are adapted to receive configuration data in th...  
WO/2007/099588A1
A clock dividing circuit includes first and second dividing circuits for dividing two-phase outer clocks (first and second outer clocks) injected from an outside to output four-phase clocks with assured phases. Each dividing circuit comp...  
WO/2007/085866A1
An amplifier having multiple gain modes comprises a plurality y of cascoded input transistors connected to an input and arranged in parallel, a degeneration stage connected to the input transistors and having a variable impedance, and sw...  
WO/2007/085867A1
A circuit for deriving an output clock signal from an input clock signal, the output clock 5 signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality...  
WO/2007/080242A1
The invention relates to a binary frequency divider (DIVF2) comprising a counter (CMPT) gated by an input signal (CK1), means (CP1, CP2) for comparing a count value (VAL) with first and second threshold values (B2/2, B2/4) and providing ...  
WO/2007/004181A3
A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at...  
WO/2007/029624A1
A dividable frequency band is widened without performing variable control of a load circuit. A master stage (101) comprises a differential circuit including a transistor (1) and a transistor (2), a differential circuit including a transi...  
WO/2007/004181A2
A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at...  
WO/2007/004183A1
A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force...  
WO/2006/135788A2
An (N-l)/N prescaler(see fig 1) is provided, where N is an S power of 2. The prescaler uses only S flip-flops,(see figure 3). The prescaler receives a clock input(101) from a high frequency oscillator and provides an output line to a cou...  
WO2006033583A3
A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This f...  
WO/2006/051490A1
The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CLl) frequency by an odd integer. A digital value is shifted into a set ...  
WO2006023250A3
A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a ...  
WO2006016310A3
A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clo...  
WO/2006/033583A2
A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This f...  
WO/2006/023250A2
A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a ...  
WO/2006/018754A1
A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(l), .., SA(N); SB(1), .., SB(N)). One multi-state circuit (MSCA) switches to a ...  
WO/2006/017519A1
A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but ma...  
WO/2006/016312A1
A frequency divider comprising, a first latch circuit (10) and a second latch circuit (10'), the second latch circuit (10') being crossed-coupled to the first latch circuit (10). Each latch (10; 10') comprises a respective sense amplifie...  
WO/2006/016310A2
A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clo...  
WO/2005/114842A1
The present invention provides for state correction of a frequencydivider. A first flip-flop is coupled to a second flip flop. A state correction circuit is coupled to the output of the second flip-flop. A third flip-flop is coupled to t...  
WO2005091506A8  
WO2004084411A8
The invention relates to a frequency divider with variable division rate, which is made using CMOS technology. The inventive divider comprises a plurality of cells (c1 to c3) which are mounted in a chain, the output of the last cell of t...  
WO/2005/114841A1
A gateless digital circuit and method for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N≤ M/2. The gateless digital circuit having a modulo M function, a register an...  
WO/2005/109643A1
A fractional frequency synthesizer includes a circuit which alternately outputs multiple output signals having different respective periods to drive the average period of the output signal to within a predetermined number of phase steps ...  
WO/2005/096501A1
Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configurati...  
WO2005086350A3
The invention relates to a frequency divider circuit (1) comprising at least one push-pull divider (T1) with an adjustable divider ratio and comprising a converter device (24), which is connected thereto and which converts a clock signal...  
WO2005091506A1  
WO/2005/091507A1
Frequency dividers (2) comprising sections (21-27) are provided with basic sections of a first type (21,23,24) for dividing frequency signals (f&ldquor ) by adjustable numbers in dependence of adjustment signals (p&ldquor ) and in depend...  
WO/2005/091506A2  
WO2005006558A3
A frequency prescaler includes true single phase clock (TSPC) flip-flops having a logic gate such as an OR-gate embedded in an input stage. This invention is described in figure 1. A precaler (100) includes flip-flops (102, 104, 106, 108...  
WO/2005/086350A2
The invention relates to a frequency divider circuit (1) comprising at least one push-pull divider (T1) with an adjustable divider ratio and comprising a converter device (24), which is connected thereto and which converts a clock signal...  
WO/2005/062470A1
A gray code is produced from a minimum of gate logic by making available and monitoring masters outputs of master-slave latch pairs, where the latch pairs are arranged to form a cascading chain of toggle flip-flop stages. The least signi...  
WO2004021355A3
An electronic device (100) has a data storage device (120) for storing N data elements, the data storage device (120) comprising a first collection (122) of data storage elements (130). The first collection (122) of data storage elements...  
WO/2005/041412A1
A prescaler, comprising a first flip-flop (F1) coupled to a second flip-flip (F2). Each flip-flop comprises a latch (M1, M2, M3, M4) having a first input (R) and a second input (S) coupled to respective first NOR circuit (M8, M9, M10) an...  

Matches 101 - 150 out of 6,228