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WO/2009/116399A1 |
A clock signal division circuit includes a mask circuit (10B) and a mask control circuit (20B). The mask circuit (10B) masks a clock pulse of a clock S in accordance with an inputted mask signal (50B) so as to generate a clock B. The mas...
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WO/2009/107105A2 |
In certain arrangements and methods, a reset-able counter (100) produces multiple delay times as required by, for example, a finite state machine. The counter (100) counts a stored value by a configurable amount. That configurable amount...
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WO/2009/095279A1 |
A local oscillator circuit for a signal transmitter or receiver, the circuit comprising: an input for receiving a master oscillating signal from a master oscillator; and signal processing circuitry configured to be clocked by the master ...
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WO/2009/021251A9 |
The invention relates to a method and a device for decreasing the frequency of a digital clock signal (A). According to the invention, the clock pulses of the digital clock signal (A) are linked with a control signal (B), which is synchr...
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WO/2009/050854A1 |
There is provided a circuit comprising a logic circuit and a current amplification circuit. The logic circuit has a first transistor disposed on the high side of a power supply and a second transistor disposed on the low side of the powe...
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WO/2009/050039A2 |
A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2,...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an...
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WO/2009/041474A1 |
An A/D converting circuit, a solid-state image sensing device and a camera system in which a counter is capable of counting on both edges of a clock as well as being switchable while keeping an up/down count, and which prevents deteriora...
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WO/2008/122958A2 |
The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting...
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WO/2008/120150A2 |
A method and a frequency dividing circuit (1) for dividing a frequency of an input clock signal (CLKin) by an odd number to generate an output clock signal (CLKout) with a lower frequency comprising at least two serially connected edge t...
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WO/2008/113105A1 |
A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received and a clock control circuit to receive the clock ...
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WO/2008/078617A1 |
Provided is a high-speed programmable synchronous counter, which realizes a programmable synchronous counter having a long word tone in a high-frequency band without using a dedicated IC, while warranting a high timing precision. The hig...
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WO/2008/065869A1 |
[PROBLEMS] To provide a rational number frequency dividing circuit wherein the variations in cycle times of frequency-divided clock signals are small, there are many occasions in which the minimum cycle time of frequency-divided clock si...
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WO/2008/056551A1 |
A rational number frequency divider circuit wherein the cycle time of a frequency-divided clock signal is constant and wherein the power consumption, layout area and design/test costs are small. A clock signal frequency divider circuit, ...
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WO/2008/044023A1 |
A spread-period clock generator (SPC) counts basic clock pulses (XK) to generate output pulses (EQ) with varying periods, and has means (controlled by signal QS) for switching between a first mode, in which counting is carried out in res...
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WO/2008/033979A2 |
Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter include...
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WO/2008/014594A1 |
An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The c...
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WO/2008/002968A1 |
A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also rece...
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WO/2007/135793A1 |
In a counter circuit (1) of a control signal generation circuit (2), a selection circuit (3) selects a predetermined signal from an HSYNC signal and a VSYNC signal as a pulse signal and inputs the same to a counter (4) in accordance with...
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WO/2007/099588A1 |
A clock dividing circuit includes first and second dividing circuits for dividing two-phase outer clocks (first and second outer clocks) injected from an outside to output four-phase clocks with assured phases. Each dividing circuit comp...
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WO/2007/085866A1 |
An amplifier having multiple gain modes comprises a plurality y of cascoded input transistors connected to an input and arranged in parallel, a degeneration stage connected to the input transistors and having a variable impedance, and sw...
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WO/2007/085867A1 |
A circuit for deriving an output clock signal from an input clock signal, the output clock 5 signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality...
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WO/2007/080242A1 |
The invention relates to a binary frequency divider (DIVF2) comprising a counter (CMPT) gated by an input signal (CK1), means (CP1, CP2) for comparing a count value (VAL) with first and second threshold values (B2/2, B2/4) and providing ...
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WO/2007/029624A1 |
A dividable frequency band is widened without performing variable control of a load circuit. A master stage (101) comprises a differential circuit including a transistor (1) and a transistor (2), a differential circuit including a transi...
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WO/2007/004181A2 |
A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at...
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WO/2007/004183A1 |
A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force...
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WO/2006/135788A2 |
An (N-l)/N prescaler(see fig 1) is provided, where N is an S power of 2. The prescaler uses only S flip-flops,(see figure 3). The prescaler receives a clock input(101) from a high frequency oscillator and provides an output line to a cou...
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WO/2006/051490A1 |
The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CLl) frequency by an odd integer. A digital value is shifted into a set ...
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WO/2006/033583A2 |
A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This f...
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WO/2006/023250A2 |
A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a ...
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WO/2006/018754A1 |
A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(l), .., SA(N); SB(1), .., SB(N)). One multi-state circuit (MSCA) switches to a ...
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WO/2006/017519A1 |
A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but ma...
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WO/2006/016312A1 |
A frequency divider comprising, a first latch circuit (10) and a second latch circuit (10'), the second latch circuit (10') being crossed-coupled to the first latch circuit (10). Each latch (10; 10') comprises a respective sense amplifie...
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WO/2006/016310A2 |
A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clo...
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WO/2005/114842A1 |
The present invention provides for state correction of a frequencydivider. A first flip-flop is coupled to a second flip flop. A state correction circuit is coupled to the output of the second flip-flop. A third flip-flop is coupled to t...
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WO/2005/114841A1 |
A gateless digital circuit and method for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N≤ M/2. The gateless digital circuit having a modulo M function, a register an...
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WO/2005/109643A1 |
A fractional frequency synthesizer includes a circuit which alternately outputs multiple output signals having different respective periods to drive the average period of the output signal to within a predetermined number of phase steps ...
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WO/2005/096501A1 |
Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configurati...
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WO2005091506A1 |
A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass fi...
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WO/2005/091507A1 |
Frequency dividers (2) comprising sections (21-27) are provided with basic sections of a first type (21,23,24) for dividing frequency signals (f&ldquor ) by adjustable numbers in dependence of adjustment signals (p&ldquor ) and in depend...
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WO/2005/091506A2 |
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WO/2005/086350A2 |
The invention relates to a frequency divider circuit (1) comprising at least one push-pull divider (T1) with an adjustable divider ratio and comprising a converter device (24), which is connected thereto and which converts a clock signal...
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WO/2005/062470A1 |
A gray code is produced from a minimum of gate logic by making available and monitoring masters outputs of master-slave latch pairs, where the latch pairs are arranged to form a cascading chain of toggle flip-flop stages. The least signi...
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WO/2005/041412A1 |
A prescaler, comprising a first flip-flop (F1) coupled to a second flip-flip (F2). Each flip-flop comprises a latch (M1, M2, M3, M4) having a first input (R) and a second input (S) coupled to respective first NOR circuit (M8, M9, M10) an...
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WO/2005/041413A1 |
A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency d...
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WO/2005/038636A1 |
An MN counter with analog interpolation (an 'MNA counter') includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input c...
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WO/2005/036751A1 |
The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable o...
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WO/2005/034358A1 |
A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first d...
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WO/2005/029720A1 |
A multi-band transceiver (100) for receiving or transmitting signals situated in substantially different frequency ranges comprising first transceiver (1) coupled to an input/output terminal (In/Out) via a first pair of switches (SWI, SW...
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WO/2005/022749A1 |
The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding functions for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry ...
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WO/2005/017540A1 |
Position detecting device, comprising a photo detection element array having n segments and a parallel arithmetic processing portion that is arranged to identify the segment having maximum intensity by comparing the output values (OV) fr...
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