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Matches 151 - 200 out of 6,231

Document Document Title
WO/2005/041413A1
A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency d...  
WO/2005/038636A1
An MN counter with analog interpolation (an 'MNA counter') includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input c...  
WO/2005/036751A1
The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable o...  
WO/2005/034358A1
A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first d...  
WO/2005/029720A1
A multi-band transceiver (100) for receiving or transmitting signals situated in substantially different frequency ranges comprising first transceiver (1) coupled to an input/output terminal (In/Out) via a first pair of switches (SWI, SW...  
WO/2005/022749A1
The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding functions for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry ...  
WO/2005/017540A1
Position detecting device, comprising a photo detection element array having n segments and a parallel arithmetic processing portion that is arranged to identify the segment having maximum intensity by comparing the output values (OV) fr...  
WO/2005/018094A1
A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (S...  
WO/2005/006558A2
A frequency prescaler includes true single phase clock (TSPC) flip-flops having a logic gate such as an OR-gate embedded in an input stage. This invention is described in figure 1. A precaler (100) includes flip-flops (102, 104, 106, 108...  
WO/2004/112251A1
A high speed CMOS phase locked loop (PLL) (10) includes a three-state phase detection circuit having a frequency phase detector (12) coupled to a charge pump (14) for monitoring the phase differences between a reference frequency signal ...  
WO2004068273A3
A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, ...) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track ...  
WO/2004/105247A1
A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of a reverse/non-reverse device (304). A connection device (306) is arranged on the feedback path (307). The feedback path (3...  
WO2004068706A3
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...  
WO2003019781A3
Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency div...  
WO2002093747A3
Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing ...  
WO/2004/084412A1
A divide-by-n process is effected via a scale-by-four/n process (110, 210, 310) followed by a divide-by-four process (120, 220, 320). A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By...  
WO/2004/084411A1
The invention relates to a frequency divider with variable division rate, which is made using CMOS technology. The inventive divider comprises a plurality of cells (c1 to c3) which are mounted in a chain, the output of the last cell of t...  
WO/2004/077676A1
The invention relates to a phase-locking circuit (1, 5, 7, 14), wherein a frequency counter (10) is provided in addition to a phase divider (5) which is preferably programmable and which is arranged in the feedback path of the PLL, said ...  
WO/2004/068273A2
A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, …) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track ...  
WO/2004/068706A2
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...  
WO2004047269A3
Dynamic flip-flop circuit comprising pass transistors (2620.4, 2624.4) and inventers (2622.4, 2626.4, 2628.4) and its application to a gray counter.  
WO/2004/047269A2
Dynamic flip-flop circuit comprising pass transistors (2620.4, 2624.4) and inventers (2622.4, 2626.4, 2628.4) and its application to a gray counter.  
WO/2004/042928A1
The invention relates to a circuit arrangement for frequency division (50), comprising a divider chain with several frequency division stages (1 to 5). The frequency divider (1 to 5) can be switched between the divider ratios 2 and 3. At...  
WO/2004/034587A1
A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-corre...  
WO/2004/032327A1
Techniques are described for producing a signal (120) having a desired frequency. The desired frequency can be produced to a very high precision, even when the desired frequency is very high. The techniques, in one example, represent an ...  
WO2003017491A3
A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.  
WO2004006436A3
A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting s...  
WO2003021785A3
A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectiv...  
WO2002101930A3
A high-speed programmable synchronous counter is disclosed. The high-speed counter includes a most-significant-bit counter synchronized with a lease-significant bit counter. The least-significant-bit counter is programmed to an initial s...  
WO/2004/021355A2
An electronic device (100) has a data storage device (120) for storing N data elements, the data storage device (120) comprising a first collection (122) of data storage elements (130). The first collection (122) of data storage elements...  
WO2002017494A3
A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and ...  
WO2002069499A3
An in-phase clock signal CLK-I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT-I is a clock signal with a...  
WO/2004/010587A1
An adder (2) and a delay device (4) constitute a 20-bit input accumulator, which is connected to a signal input terminal (1). An adder (8) and a delay device (10) constitute a 9-bit input accumulator. The most significant 8 bits of outpu...  
WO/2004/006436A2
A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting s...  
WO/2003/105347A1
A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use ...  
WO2002054593A3
A digital frequency multiplier provides no-integer frequency multiplication of an input signal. A multiplier receives the input signal and an integer multiple of the input signal. A multiplier control signal selects/toggles which signal ...  
WO2002052728A3
The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regi...  
WO/2003/094353A1
A high speed programmable counter architecture is disclosed (208). In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler (304) and an m bit low speed counter...  
WO/2003/079551A1
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler(P, P+1) and two counters (R and Q) by interleaving the division moduli. Within a given cycle, 'ones' and 'tens' are not all c...  
WO/2003/058817A1
A prescaler circuit comprising n DFF circuits (n≥3); a first multi-input logic gate circuit having two or more inputs; and a second multi-input logic gate circuit, wherein the output terminals of the first multi-input logic gate circui...  
WO/2003/043193A1
A programmable−divider provides a lower−speed transition signal to effect a synchronized load of a new divisor value during a safe−load period of the programmable−divider, such that the division occurs using either the prior divi...  
WO/2003/032495A1
The invention concerns a dual-mode divider counter circuit for a frequency synthesizer comprising several 1:2 dividers of asynchronous type connected in series, a phase selector block (11) interposed between two of the 1:2 dividers (10, ...  
WO/2003/021785A2
A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectiv...  
WO/2003/019781A2
Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency div...  
WO/2003/017491A2
A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.  
WO/2003/005588A1
A frequency divider device including: a divider input: a phase count and select section including: at least two phase count and select inputs each communicatively connected to the divider input, for receiving each at least one phase shif...  
WO2002080369A3
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...  
WO/2002/101930A2
A high-speed programmable synchronous counter is disclosed. The high-speed counter includes a most-significant-bit counter synchronized with a lease-significant bit counter. The least-significant-bit counter is programmed to an initial s...  
WO/2002/093747A2
Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing ...  
WO/2002/082652A2  

Matches 151 - 200 out of 6,231