Document 
Document Title 
WO/2002/080369A2 
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...

WO/2002/071614A1 
A frequency synthesizer (200) is provided that allows for a halfcycle division of the synthesized frequency. In a conventional sigmadelta fractionalN frequency synthesizer, a controllable divider is configured to allow for the divisio...

WO/2002/069499A2 
An inphase clock signal CLK$m(Y)I drives a first pair of connected data flipflops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an inphase OR gate (320). The output signal OUT$m(Y)I is a clock signa...

WO2002029973A3 
A programmable divider includes a synchronous counter (202) configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices (210, ...,21N) are coupled to the sync...

WO/2002/054593A2 
A digital frequency multiplier provides nointeger frequency multiplication of an input signal. A multiplier receives the input signal and an integer multiple of the input signal. A multiplier control signal selects/toggles which signal ...

WO/2002/052727A1 
Apparatus comprising a frequency dividing cell (42) with a prescaler logic, an endofcycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency f...

WO/2002/052728A2 
The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regi...

WO2001091298A3 
A fractional divider divides an input frequency of a first signal (Fi) by a rational, nonintegral number, which rational number is greater than one and, when written as vulgar fraction, can only be written with a denominator not equal t...

WO/2002/035706A1 
This invention relates to a prescaler comprising a pulse swallow circuit in series connection with a divider circuit providing a fixed division ratio, wherein the pulse swallow circuit comprises the input of the prescaler and a control i...

WO/2002/029973A2 
A programmable divider includes a synchronous counter (202) configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices (210, ...,21N) are coupled to the sync...

WO/2002/023725A1 
A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a lookahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of sa...

WO/2002/017494A2 
A graycode counter system (AP1) for a RAMbased FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a graycode decoder (11), a binary incrementer (12), a graycode encoder (13), and ...

WO2001065681A3 
A phaselocked loop has a phase detector (501) that generates a phase difference signal, a circuit (505) that generates a phaselocked loop output signal having a frequency that is a function of the phase difference signal, a frequency d...

WO/2001/093427A1 
This invention relates to a CMOS prescaler device for frequency dividing a high frequency signal, said device having two operating modes providing two different divisional ratios and comprising: a first fixed division ratio divider havin...

WO/2001/091298A2 
A fractional divider divides an input frequency of a first signal (Fi) by a rational, nonintegral number, which rational number is greater than one and, when written as vulgar fraction, can only be written with a denominator not equal t...

WO/2001/084710A1 
The power consumption of a frequency divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lo...

WO/2001/080426A1 
A PLL circuit comprises means (3) for generating a plurality of reference signals (fR1fR8) of different phases, a primary divider (30) for dividing the output signal (fVCO) from a voltagecontrolled oscillator (29) by a factor N1, a sec...

WO/2001/065681A2 
A phaselocked loop has a phase detector (501) that generates a phase difference signal, a circuit (505) that generates a phaselocked loop output signal having a frequency that is a function of the phase difference signal, a frequency d...

WO/2001/054282A1 
The present invention relates to a frequency divider having an adjustable divider ratio (TV). Such circuits are subject to requests for ever higher clock frequencies. For fulfilling said requests, the inventive circuit generates the outp...

WO/2001/050610A1 
A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite ph...

WO/2001/045263A1 
A method and system described for producing frequency multiplication/division by any noninteger output signal frequency relative to a reference signal frequency of a PhaseLockLoop (PLL), while simultaneously maintaining low jitter. In...

WO/2001/033716A1 
Nonpoweroftwo greycode counters (AP1, AP4, AP5, AP6), including modulos10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register (REG, 402, 502, 602) for storing an Nbit, e.g., 4...

WO/2001/015323A1 
A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer...

WO2000025426A8 
A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter (12) for monitoring a number of specified events. A data storage device (14) is coupled to the counter (12) for l...

WO/2001/013520A1 
Method for frequency distribution, especially for highfrequency synthesis using a phaseregulating or frequencyregulating loop via counting device (19, 25). Frequency is adjusted by means of a control word, whereby an addend (S) for th...

WO/2001/011784A1 
The invention relates to a frequency synthesiser which functions on the principle of fractional frequency synthesis. It consists of an integral frequency divider which can be regulated, and a control device in which a desired broken frac...

WO/2001/010028A1 
The present invention, generally spreading, achieves noise spreading within a PLL using a dualmodulus prescaler by interleaving the division moduli. Within a given cycle, 'ones' and 'tens' are not all counted consecutively. Instead, one...

WO2000025426A9 
A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter (12) for monitoring a number of specified events. A data storage device (14) is coupled to the counter (12) for l...

WO2000019611A9 
A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a masterslave flipflop. An input clock signal having a frequency FN is supplied to the flipflop of each circuit block, an...

WO1998039845A3 
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input a...

WO/2000/030259A1 
A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a singlephase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay...

WO/2000/025426A1 
A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter (12) for monitoring a number of specified events. A data storage device (14) is coupled to the counter (12) for l...

WO/2000/019611A1 
A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a masterslave flipflop. An input clock signal having a frequency FN is supplied to the flipflop of each circuit block, an...

WO/2000/008790A1 
Either a set of frequency divisor data representing at least one frequency divisor which is an integer larger than the ratio (fa/fb) of the frequency (fa) of an input clock to a target frequency (fb) of the output clock or a set of frequ...

WO/2000/008761A1 
A rational frequency divider for producing an integer frequency from a rational frequency, consisting of a memory for storing first and second divider constants; a selector device for selecting the stored divider constants; a first count...

WO/2000/001071A1 
The invention relates to a static frequency divider with a modifiable divider ratio for maximum frequencies and with a minimal overall power consumption. In a first divider stage, a Tflipflop is provided with modified Dflipflops whic...

WO/1999/060702A1 
A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line ($i(en)), including a number of counter blocks, corresponding to the number of bits of the counter, connected in series. Th...

WO/1999/050793A1 
A counting device, comprising: an input (105, 107) for receiving an input signal having at least three distinct input states; memory means (810) for storing a count; and means (620) responsive to a predetermined sequence of input states ...

WO1999018668A3 
A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an ...

WO/1999/031805A1 
A multidivide frequency divider, includes a chain of seriallyconnected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a freq...

WO/1999/027651A1 
A circuit is disclosed for sampling analog signals at a rate which is a rational, noninteger fraction of a clock frequency. The analog signal is sampled at nonequidistant sampling points, with the distances between successive points fo...

WO/1999/022449A1 
A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (...

WO/1999/018668A2 
A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an ...

WO/1999/018669A1 
The invention concerns the field of variable modulo frequency dividers. In order to obtain a quick variable modulo on a wide operating range the invention proposes the use of twin flipflops (1, 2; 3, 4; 5, 6; 7, 8) for feedback's. The a...

WO/1999/003207A1 
The invention relates to a digital phase locked loop for synchronizing an output clock signal with a reference clock signal, comprising a numerically controlled oscillator (2), which can be programmed, specially in relation to a desired ...

WO/1998/039845A2 
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input a...

WO/1998/020407A1 
In a semiconductor integrated circuit provided with a clock generating circuit using a PLL circuit and a serial communication circuit, a clock having a frequency which is a power of 2 is inputted into the clock generating circuit as a re...

WO/1998/015061A1 
The subjectmatter of the application relates to a device in which a highfrequency clock signal (CLK8) can be converted to a lowfrequency clock signal (CLK5) whereby a strobe signal (STI) is shifted through a shift register (Reg 1....R...

WO/1998/009379A1 
A frequencydividing circuit comprises a digital accumulator capable of performing signed arithmetic and means for adding of a predetermined numerator to the content of the accumulator. Means are provided for subtracting a predetermined ...

WO/1997/049186A1 
The invention relates to fast serialparallel and parallelserial converters, and in them included frequency dividers. The serialparallel converter comprises a shift register (51), an output register (52) and a frequency divider (40). T...
