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Patent Searching and Data


Matches 251 - 300 out of 6,226

Document Document Title
WO/1996/037962A1
An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the d...  
WO/1996/030821A1
In a clock generator for supplying clocks to a unit (31) operating by a high speed clock CLK0 or a low speed clock CLK1 and to a unit (32) operating by CLK0 or CLK1, a variable clock generator of this invention includes a switch signal c...  
WO/1996/021278A1
A counter system has a first counter (1) seeded by several input signals and a second counter (2) seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an ...  
WO/1996/015484A2
A monolithic integrated circuit for providing enhanced audio performance in personal computers is disclosed. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit (CODEC) including an...  
WO/1995/021078A1
The proposal is for a device for operating a windscreen wiper in intermittent and continuous modes. To this end, there is at least one sensor (12) emitting signals depending on the degree of wetting or quantity of rain on a windscreen to...  
WO/1995/020269A1
A phase-locked-loop frequency synthesizer with adjustable frequency has a signal source of predetermined reference frequency of 10, 100 or 1,000 Hz, and a comparator with a first input receiving the reference frequency signal, a second i...  
WO/1993/013601A1
A high resolution digitally controlled oscillator is in the form of a digital frequency divider (10), which uses calculation logic (14) to utilize both the rising edge and the falling edge (start edge and stop edge) of the input clock pu...  
WO/1992/011589A1
A pulse frequency divider for two opposed pulse trains comprises an up/down counter and a comparator which tracks the net counts of the combined (and oppositely sensed) pulse trains. Means are provided for separating the counting loop po...  
WO/1991/018449A1
A scaler comprising a plurality of flip-flops (31-34), varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop (31-34) is continuously and synchronously responsive to either a rising (31, 33) or a falling (32, 3...  
WO/1991/011726A1
A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).  
WO/1991/011860A1
A frequency divider (10) receives a first frequency signal (CKT) and at least one clock signal (CKI) of a sub-multiple of the first frequency. The first frequency signal (CKT) charges a storage terminal (42) once each first frequency cyc...  
WO/1991/002410A1
An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider (4), second divider (5), synchronization circuit (6) for providing a first modulus control signal (7) to...  
WO/1990/008428A1
A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages (outputs at 10, 12, 14, 16, 18). When a modulas control signal (MC) is low, the prescaler operates as five clocked invert...  
WO/1990/007232A1
A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmab...  
WO/1990/005413A1
A high speed digital programmable frequency divider (10') capable of frequency division by even and odd integers is disclosed herein. The frequency divider (10') of the present invention includes a waveform generator (20') for providing ...  
WO/1990/001832A1
An N stage Gray code counter includes an N stage binary counter (11-14) having an input for receiving clock pulses to be counted and providing N outputs (B0-B3) forming an N bit binary code. N minus 1 storage stages (21-23) capable of be...  
WO/1989/010028A1
In a logic network consisting of a number of cascode connected modules (TF) for processing digital signals, carry signals which propagate as a ripple signal from one module to another often represent a serious limitation as regards the m...  
WO/1989/005546A1
A D-type, master-slave, flip-flop is described for use as a divide-by-two frequency divider in which a frequency to be divided is input as a clock signal and the Q output is connected to the D(Boolean not) input, and in which the master ...  
WO/1988/000775A1
An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (CSU) (14). The CSU (14) comprises a row o...  
WO/1987/005453A1
A counting circuit which counts the number of pulses asynchronously input during a predetermined period of time includes a counter (C') which counts the number of input pulses, a register (D) which stores the pulses emitted from the coun...  
WO/1987/000365A1
A frequency dividing arrangement (5) comprises a frequency divider (6) coupled to an active filter (7) which is operative to suppress output radiation from the frequency dividing arrangement. The arrangement (5) may be incorporated into ...  
WO/1986/003633A1
A method and apparatus for dividing a clock pulse frequency Cl in a ratio A/B, where the quotient between B and A is the whole number C and the remainder D. A pulse train is generated, which includes (A-D) half pulses with a pulse length...  
WO/1986/003078A1
A logic circuit for use in a variable frequency divider (8) includes a driver (T1, T2), a latch (T3, T4), and an enabling switch (T5, T6) each comprising a pair of emitter coupled transistors. The driver (T1, T2) is coupled to the latch ...  
WO/1986/002793A1
A frequency divider (50) for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate (51) ...  
WO/1986/002216A1
A counter apparatus which counts the number of pulse signals and outputs on ON/OFF state previously stored at an address corresponding to the count thereof. When a signal corresponding to a set mode is output from a mode changeover devic...  
WO/1986/000985A1
An electronic odometer (10) which is field presettable within limits after it is installed in a vehicle. A microprocessor (14) is utilized to store a total accumulated mileage (odometer) signal in a non-volatile random access memory (RAM...  
WO/1985/004297A1
A counting apparatus wherein an output indication is provided in response to a predetermined number, N, of input voltage or current transitions. The apparatus is constructed with a plurality of subcounters each one of which responds to t...  
WO/1985/003176A1
An improved multiple frequency digital phase-locked loop circuit (10). The improved digital phase-locked loops utilizes a single circuit (12) to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loo...  
WO/1984/003406A1
An I2L non-integer programmable counter that has a high frequency precision that uses feedback to adjust count length. A first divider (12) adapted to receive a clock signal (FCL) having a first frequency and an input signal, provide a s...  
WO/1983/003502A1
The design of a system is simplified by making control lines from a microprocessor as small as possible when the frequency-dividing ratio of a programmable divider of a phase-locked loop is controlled by an up/down counter. This circuit ...  
WO/1982/003477A1
A frequency synthesized transceiver capable of tuning to a plurality of communication channels. The transceiver includes a receiver section (72) and a transmitter section (74) which are coupled to the synthesizer which generates the appr...  
WO/1982/002464A1
A clock rate generator which can be programmed to provide an output clock that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter (20), a programmable memory (30), reset logic (40) and...  
WO/1981/002372A1
A high frequency divider suitable for use in a frequency synthesizer using a dual modulus prescaler (10) and two counters (30, 40) to achieve high speed and low current drain. The input signal is alternately divided by one of the two mod...  
WO/1981/002371A1
An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler (132) of limited ...  
WO/1981/002080A1
A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge trans...  
WO/1981/000472A1
An increment/ decrement circuit which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/ decrement circuit and also uses a reduced number of transistors. The increment/ decre...  
JP6524540B2  
JP2019512195A
A local oscillator is provided with a voltage controlled oscillator, a multi stage counting-down circuit including the 1st step and the 2nd step, and a duty cycle converter in some modes. The output node of a voltage controlled oscillato...  
JP2019057281A
[Subject] A clock generation circuit which makes it possible to generate a clock of desired frequency immediately is provided. [Means for Solution] In semiconductor device 100, clock control module 10 possesses PLL circuit 1 and counting...  
JP6482032B2  
JP6463169B2  
JPWO2017154191A1
The 1st part circumference way part (10) that Divide the 1st clock signal and generates the 1st Divide clock signal, The 2nd part circumference way part (20) that Divide the 2nd clock signal that has the 1st phase contrast on the same fr...  
JP6454619B2  
JP6437142B2  
JP2018164151A
To provide a high-quality frequency divider circuit.A frequency divider circuit comprises: a first flip-flop having a first input end to which a clock signal is inputted as well as a second input end to which a first signal is inputted; ...  
JP2018160817A
To provide a counter circuit, a measuring device, and a physical quantity sensor, capable of reducing a through current when a carry-over occurs and which can make the circuit configuration simple and small scale.The counter circuit incl...  
JP2018528675A
A method and a device for synchronizing the counting-down circuit within a different LO course using PAL Susurou . The 1st course that has the 1st counting-down circuit constituted so that one exemplary device might generally generate th...  
JP6387896B2  
JP2018137681A
To suppress a residual jitter when forming a strove while capable of using a fixed BPF for a passing frequency range.A trigger circuit 2 includes: a DDS 12 that outputs a trigger clock input within a movable frequency range at an arbitra...  
JP6379627B2  

Matches 251 - 300 out of 6,226