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Matches 301 - 350 out of 6,231

Document Document Title
JP2018528675A
A method and a device for synchronizing the counting-down circuit within a different LO course using PAL Susurou . The 1st course that has the 1st counting-down circuit constituted so that one exemplary device might generally generate th...  
JP6387896B2  
JP2018137681A
To suppress a residual jitter when forming a strove while capable of using a fixed BPF for a passing frequency range.A trigger circuit 2 includes: a DDS 12 that outputs a trigger clock input within a movable frequency range at an arbitra...  
JP6379627B2  
JP6375317B2  
JP2018520577A
The circuit for a separator or a counter divides input frequency (Vin), and may contain the frequency divider which has a plurality of rings for acquiring an output frequency. The 1st and 2nd rings may contain a plurality of elements of ...  
JP2018518886A
At an example, it is a phase lock loop (PLL) circuit (108), It is based on the error detector (202) which can operate, and an error signal and a frequency band selection signal so that an error signal may be generated, The oscillator (20...  
JP6344979B2  
JP2016163156A5  
JPWO2017158761A1
Among a plurality of dual modulus counting-down circuits (1*1, 1*2) which a setting data output circuit (3) can set in the 1st counting-down circuit group (1), It constitutes so that setting data may be updated from a reset circuit (6) s...  
JP2018042167A
To suppress generation of fluctuations in delay time of a frequency divided clock caused by temperature fluctuations.A clock generating circuit 1 includes: a frequency divided part 16 generating a frequency divided clock of a frequency 1...  
JP2018504819A
A variable frequency part circumference device provides the signal acquired by dividing the frequency of the signal inputted by variable number D, and is provided with the 1st counter, the 2nd counter, and a controller. The 1st counter m...  
JP2018026620A
To realize reduction of circuit scale and shortening of free run frequency correction time.A PLL circuit including a phase comparator 1, a charge pump circuit 2, a lowpass filter 3, a VCO4, an injection synchronous VCO6, an injection syn...  
JP2018019221A
To provide a frequency division correction circuit, a receiving circuit, and an integrated circuit that can generate a decimal frequency division signal with a duty ratio of 50% without using a four-phase clock.A frequency division corre...  
JP6268020B2  
JP2018006900A
PURPOSE: To provide a radio communication device about which both reduction in circuit scale and reduction in power consumption are efficiently achieved.CONSTITUTION: A signal generation circuit includes: a PLL (Phase Locked Loop) synthe...  
JP2017228894A
To provide a programmable frequency divider, a PLL synthesizer and a radar apparatus capable of achieving stable operation independently of temperature variation, voltage variation, process variation, and so on.A pulse swallow type progr...  
JP6254394B2  
JP6254465B2  
JP6234545B2  
JP2017181463A
To make it possible to adjust a bias voltage of a frequency divider circuit even without using an external measuring instrument.A first frequency divider circuit 112 is configured to divide a clock signal oscillated from an oscillation c...  
JP2017168969A
To provide a technology for integrating a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources.A counter circuit 8 comprises: JK type flip flops FF in a plurality of stages; a...  
JP2017147692A
To provide a histogram counter having no count operation disabled period, and a small circuit area, and to provide a radiation detection circuit.A histogram counter includes a first lower bit counter 2A, a second lower bit counter 2B, an...  
JP2016525301A5  
JP6145195B2  
JPWO2016027329A1
It is generating several Divide clock signals which connect by turns the latch circuitry driven in the standup of a clock signal, and falling and with which phases differ based on the combination of the level of the output of a plurality...  
JPWO2015136659A1
In a PLL circuit (1001), first, output voltage Vtune of LPF (50) is connected to ILFD (10 (n)), and ILFD (10 (n)) serves as an oscillator. ILFD (10 (n)), DIV (20), PFD (30), CP (40), and LPF (50) constitute PLLn, and a locking action beg...  
JP2017508358A
a plurality of calculation -- a counter which can include a stage is indicated. a ferroelectricity capacitor with which a total of several steps are characterized each by the 1st and 2nd polarization states, a variable impedance componen...  
JP6092337B2  
JP2017034622A
To reduce a frequency error, to enable a smooth frequency change and to enable pulse output improved in responsiveness.A pulse output device comprises: a prescaler P0; a timer T1 of (n) bits ((n) is a value of a square of 2 and equal to ...  
JP2016208452A
To obtain a frequency divider that can suppress the occurrence of glitch even if the timing of the control signal is shifted.The frequency divider of the present invention includes a divide-by-2 circuit for dividing a frequency of an inp...  
JP6029747B2  
JP6028052B2  
JP2016181319A
To provide a semiconductor device that achieves better operation.A semiconductor device comprises a first transistor and a second transistor electrically connected to a gate of the first transistor. The first transistor has a first termi...  
JP6005441B2  
JP2016171320A
To reduce the number of transistors connected to a capacitor.A semiconductor device includes a capacitor and a transistor. One electrode of the capacitor is connected to a wire and the other electrode of the capacitor is connected to a g...  
JP2016163156A
To provide a technique advantageous in making fast transmission of a signal while suppressing increase in a circuit area.An electronic circuit comprises a generation circuit which generates a first signal group and a second signal group,...  
JP5976685B2  
JP5974863B2  
JP2016525301A
A counting-down circuit (300) which has duty cycle adjustment in a feedback loop is indicated. In an exemplary design, a device includes at least one part circumference way (310a, 310b) and at least one duty cycle equalization circuit (3...  
JP5954077B2  
JP2016129342A
To provide a frequency divider capable of operating at a high speed, and a phase-locked loop.A frequency divider 200 includes: a lowest significant (LS) step 220; a plurality of divider steps 230-1 to 230-N which is cascaded; and an outp...  
JPWO2014017472A1
A clock signal which Division a reference clock signal and has target average frequency with a clock signal generating device is generated. A reference clock signal is specifically Division (ed) by the 1st minute circumference ratio equi...  
JP2016122897A
To provide a divider circuit capable of achieving stability of a division operation by suppressing fluctuations in a self oscillation frequency of a flip-flop circuit due to variations in manufacturing transistors for sample or fluctuati...  
JP5932009B2  
JP5928590B2  
JP2016092840A
To provide a gray counter and an analog-digital converter using such a counter.In an N bit gray counter including a series of N logic cells (CL-CL) connected in cascade, where N is an integer larger than 1, each logic cell includes a cir...  
JP2016076915A
To provide a frequency synthesizer that can be switched fast and is small in the number of unnecessary frequency components in an output frequency signal.In a frequency synthesizer 1, a DDS 2 which operates based upon a clock signal gene...  
JP5914718B2  
JP5893026B2  

Matches 301 - 350 out of 6,231