Pulse Technique

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Document	Document Title
JP5571185B2	The frequency counting-down circuit by the 分周 ratio which can be set up A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clock...
JP2014135550A	CLOCK GENERATION CIRCUIT To generate a clock signal of 256 fs having a constant time interval from a signal rise to the next signal rise from a clock signal of 192 fs.An input clock signal CK1 with a constant duty ratio is doubled in frequency to generate a cloc...
JP5557905B2	A clock detecting method and its device The present invention provides a method and apparatus for clock checking, in order to solve the problem of high resource occupation in existing clock checking methods. The method includes: a programmable device for performing frequency d...
JP5530687B2	Manufacturing method of semiconductor device To reduce current consumption in a frequency-division circuit, particularly in a multistage frequency-division circuit, in a multistage frequency-division circuit, an inputted signal has a higher frequency in a preceding stage, and an in...
JP5524416B2	Parallel path frequency divider circuit A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second porti...
JP5522050B2	Clock divider circuit, clock divider circuit, clock divider method and clock divider method To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit ac...
JP5524216B2	Latch structure, frequency divider, and how to operate them A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (...
JP5516299B2	Divider and mixer circuit with it A divider has a clock generation circuit which combines a first trigger clock and a second trigger clock having a first phase difference, so as to generate a third clock having pulse edges corresponding to pulse edges of the first trigge...
JP5521061B2	Semiconductor devices, display devices, and electronic devices To provide a circuit which inhibits shift of a threshold voltage of a gate electrode of a transistor which is easy to deteriorate and shift of a threshold voltage of a turned-on transistor, and provide a driving method of the circuit in ...
JP5512816B2	2-divided injection lock ring oscillator circuit A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circui...
JP2014099238A	SEMICONDUCTOR DEVICE To provide a counter circuit capable of rightly counting a high frequency signal in which hazard or the like may easily occur.A counter circuit comprises: a frequency divider circuit 100 for generating frequency-divided clocks LCLKE and ...
JP5494858B2	Clock signal divider circuit and clock signal divider method To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test cos...
JP5488470B2	Clock divider circuit, clock divider circuit, clock divider method and clock divider method A clock frequency divider circuit 11 according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by masking (S-N) clock pulses from S clock pulses of the input cl...
JP5493591B2	Clock divider circuit and method
JP5494063B2	Control device and image forming device A control device for generating a second trigger with a delay of a predetermined time from generation of a first trigger, the control device having: a counter for counting numbers from 0 to n-1 at a frequency with cycles of a first perio...
JP2014086951A	FREQUENCY-DIVIDED PULSE GENERATION CIRCUIT To implement a high frequency operation and generate a high precision frequency-divided pulse.A frequency-divided pulse generation circuit 11 for dividing the frequency of a clock CK to be frequency-divided to generate a frequency-divide...
JP5466860B2	Divider
JP5456275B2	A counter circuit, a latency counter, a semiconductor storage device including the counter circuit, and a data processing system. To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing cloc...
JP5438055B2	CDR circuit
JP5407087B1	Fractional divider circuit To provide a fractional frequency dividing circuit capable of reducing jitter by arranging clock edges with less bias. In the fractional frequency dividing circuit 10 of the present invention, when the quotient of CTS / N is CTSquo and t...
JP2014021786A	COMPUTER SYSTEM To provide a computer system including a CPU with an L2 cache, a bus master device and bus slave devices, which are connected via a system bus to communicate with each other.A computer system 100 includes: a transaction monitor 60 for mo...
JP5386026B2	Control signal generation circuit and semiconductor device using it To provide a control signal generating circuit suitable for controlling a semiconductor device.A Johnson counter 31 includes flip-flops FF1-FF4 and gate circuits 41-44. It changes control signals C1-C4 to an "H" level in response to star...
JP5372114B2	Divider circuit and PLL circuit A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even n...
JP5355401B2	Pulse counter with clock edge restoration An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The c...
JP5346741B2	A shift register, a gate driver having the shift register, a liquid crystal display device, and a method of generating a pulse as a gate drive signal. A gate driver for use in a liquid crystal display has a plurality of shift registers connected in series. Each of the shift registers is used to provide a gate-line pulse to a row of pixels in the liquid crystal display. The gate-line pu...
JP5338819B2	Clock divider circuit and clock divider method A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by ...
JP5343966B2	Clock signal divider circuit and method A mask circuit (10) masks the clock pulses of a clock S in accordance with an input mask signal (50), generating and outputting a clock B. A mask control circuit (20) generates a mask signal (50) which assigns mask timings to mask (M−N...
JP5332616B2	Clock signal divider circuit A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an inpu...
JP5303757B2	Timing generation circuit To provide a circuit technology capable of finely setting transition timing in a relevant level of a processing objective signal which has a constant or a variable period, and is transited at least in two levels during one period. A timi...
JP5307157B2	Digital logic circuits, shift registers, and active matrix devices A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power...
JP5272627B2	Semiconductor integrated circuits, communication devices Disclosed is a semiconductor integrated circuit for generating a frequency division clock signal that approximates a desired clock signal without increasing a size thereof. The semiconductor integrated circuit masks, for each programmabl...
JP5261956B2	Bidirectional shift register To provide a shift register in which shift register operation can be achieved in a small chip area and which can be operated only by rise (or fall) edge of a clock input. When a control signal CK(36) is low and a control signal CKb(37) i...
JP5259823B2	Trisection Quadrature Phase Frequency Divider A local oscillator circuit, comprising a timing circuit configured to provide an in phase signal and a quadrature phase signal; a delay circuit configured to delay the in phase signal, thereby producing a delayed in phase signal; and a f...
JP5240850B2	Clock signal divider circuit and clock signal divider method To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test cos...
JP5228553B2	Clock signal divider circuit and method
JP5223696B2	Clock divider circuit and clock divider method
JP5223704B2	Dual modulus prescaler To increase a setup margin and to perform an operation at a higher speed. The dual modulus prescaler includes 9 pieces of flip-flops U12, U4-U11 cascade-connected in a ring shape and a NAND gate U3. The flip-flops U12, U4-U11 are arrayed...
JP5216945B1	Semiconductor device An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor ...
JP2013115690A	CLOCK FREQUENCY DIVISION CIRCUIT To provide a clock frequency division circuit (1) with an n-bit counter which outputs frequency-divided outputs at constant timings irrespective of a division ratio.A decoder (4) serves to select a desired division ratio 1/m, and an n-bi...
JP2013077868A	PLL CIRCUIT To provide a TDC capable of eliminating a need for correcting a digital code for the purpose of compensating variation in delay time of a delay element.A PLL circuit has: an oscillation part outputting an output signal having a frequency...
JP5187618B2	Counter device
JP5190549B2	Semiconductor devices and electronic devices An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor ...
JP5184680B2	A frequency divider circuit, a PLL circuit equipped with it, and a semiconductor integrated circuit
JP5180627B2	Counter circuit A system includes a memory and a counter circuit associated with the memory and configured to receive a clock signal and a plurality of input bits, and configured to output a plurality of output bits to the memory. The counter circuit in...
JP5173618B2	Shift register and its drive method and liquid crystal display panel drive A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first cloc...
JP5157461B2	Dividing circuit and dividing method
JP2013046094A	REFERENCE SIGNAL GENERATION DEVICE To provide a reference signal generation device that generates a desired reference signal from a plurality of external reference signals without requiring an increase in circuit scale, and outputs a stable reference signal even in an unl...
JP2013042244A	OSCILLATION CIRCUIT AND ELECTRONIC APPARATUS USING THE SAME To reduce a spectral peak.An oscillation circuit 2 receives a reference clock signal CKREF to generate an output clock signal CKOUT. A programmable frequency divider 18 whose frequency division ratio is switchable to at least two values ...
JP5151587B2	Clock signal divider circuit and method
JP2013034174A	ELECTRONIC APPARATUS To regulate a clock signal with high precision.An electronic apparatus includes: a first frequency division section 1162 for dividing the frequency of a clock signal by a first division number; a second frequency division section 1163 fo...

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