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Patent Searching and Data


Matches 401 - 450 out of 4,634

Document Document Title
JP5114218B2
In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal ha...  
JP2012256056A
To provide a semiconductor circuit operating correctly as a shift register without a level shifter while reducing the number of transistors included in the circuit.A display device includes m stages (m is an arbitrary positive integer sa...  
JP5097573B2
Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF ...  
JP2012244290A
To provide a phase comparison circuit that implements phase difference detection at a range of ±180 degrees even if a frequency ratio of input signals is not an integer.The phase comparison circuit comprises: a phase comparison core cir...  
JP5089820B2
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal outpu...  
JP5091911B2  
JP5090324B2
The circuit (1) has two NAND gates (15, 16) arranged in negative feedback between two dynamic D-type flip flops (12, 13) which are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency is matched w...  
JP5082952B2  
JP2012222793A
To provide a variable frequency division device that is compliant with a fast clock signal.A variable frequency division circuit 101 inputs a clock signal Clk_a, and outputs a signal Do1 that is a frequency division of the clock signal C...  
JP5059828B2
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...  
JP5044719B2
Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from...  
JP5035071B2
To relax a trade-off relation between a high-speed operation and a wide operating frequency range of an apparatus, in a frequency divider utilizing a current logic type flip-flop circuit. A latch pair part L is divided into a first latch...  
JP5028524B2
A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the referenc...  
JP2012521669A
A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a ...  
JP2012169891A
To provide a counter circuit that performs double precision measurement while using a smaller circuit scale and/or lower power consumption than before.The counter circuit includes: a first circuit for counting pulses in synchronism with ...  
JP5015090B2
The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in ...  
JP5005821B2
A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2, ...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of a...  
JP4996425B2
To provide a digital counter, a timing generator, an imaging system, and an imaging apparatus which can reduce the periodic power supply noise, accompanying the counting operation. The digital counter performing count operation by Gray c...  
JP4988840B2
A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also rece...  
JP4979202B2
A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetric...  
JP4977717B2
A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality o...  
JP2012129643A
To implement a PLL circuit for generating a signal with a slight frequency change while relatively reducing a signal frequency division rate and suppressing an increase in phase noise.A clock frequency control circuit includes: a voltage...  
JP4967400B2  
JP4965866B2
A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory elem...  
JP4956434B2
A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This f...  
JP2012113812A
To reduce the power consumption of a shift register unit by reducing a momentary current.The shift register unit includes: an input module which receives a first clock signal, a second clock signal, a frame start signal, a high-voltage s...  
JP4927301B2
A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of sa...  
JP2012039296A
To provide a counter circuit where jitters are equivalent to those of a synchronous type counter, the counter circuit making it possible to change the pulse width of the output wave of an output signal.The counter circuit comprises: shif...  
JP2012014183A
To provide a driving circuit of a semiconductor display device, that can provide an excellent image with high definition and high resolution without image unevenness regardless of the variation in TFT characteristic, and to provide a sem...  
JP4856458B2
The frequency divider includes the buffer 30, the function selector 31 and the inverter 32. The output of the function selector 31 is input to the buffer 30. The output of the buffer 30 is fed back to the function selector 31 by two path...  
JP2012501110A
In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse ...  
JP4851956B2
To provide a semiconductor integrated circuit capable of highly accurately inspecting a clock signal even when the clock signal has a high frequency. A semiconductor integrated circuit is provided which is characterized in including a pl...  
JPWO2010004747A1
Inverted data signal using, for example, two clock signals out of eight-phase clock signals so as to provide a frequency divider circuit for the multi-phase clock signal that can secure sufficient data latch time even for a multi-phase c...  
JP2011250057A
To provide a divider circuit which can generate and output a phase synchronized output signal and inverted signal thereof.A divider circuit 1 consists of a clock signal generation part 10, a frequency-divided signal generation part 20, a...  
JP4833241B2  
JP4816953B2
To make shift data of a shift register be reliably latched by a latch circuit without errors even when a reference clock signal is sped up. A load element drive circuit device 10A has a counter 16A for outputting an enable signal enable ...  
JP4792272B2
To solve a problem of a conventional differential latch that an unstable operation begins when an input amplitude gets smaller due to the effect of a high speed operation or the like. A plurality of threshold values of longitudinally sta...  
JP4780144B2
Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving t...  
JP2011188026A
To reduce power consumption by reducing an operation voltage in a clock frequency divider circuit.The clock frequency divider circuit includes: a counter for counting an input clock signal to form a D-ary count value; a counter for count...  
JP2011182364A
To provide a CMOS inverter type high-frequency divider with low current consumption for use in radio communication devices and the like.The divider includes a first to fourth inverter 4, 5, 6, and 7 with a latch function each of which in...  
JP4763049B2
In a counter circuit of a control signal generating circuit, a selector circuit selects under control which is in accordance with a selector circuit control signal (CTR) a predetermined one in a signal VSYNC and a signal HSYNC, which are...  
JP2011164688A
To reduce power consumption of a cumulative addition circuit.The cumulative addition circuit includes an addition circuit, a counter, and a clock gating control circuit. The addition circuit performs cumulative addition of data of prescr...  
JP4756135B2
A frequency divider comprising, a first latch circuit and a second latch circuit, the second latch circuit being crossed-coupled to the first latch circuit. Each latch comprises a respective sense amplifier coupled to a respective latch....  
JP4743227B2
To keep continuity of count values when switching count modes in an asynchronous counter circuit capable of switching count modes. In an A/D converting method, between flip-flops 410, three-input and one-output type three-value switching...  
JP2011151672A
To frequency-divide an input pulse train changing a period, and to suppress the jitter of the frequency-divided pulse train as much as possible.A frequency division device 1 takes a positive integer having mutually different first variab...  
JP2011151476A
To provide a synchronization circuit capable of correctly synchronizing a counter of an arbitrary value using gray codes, while suppressing increase of a circuit scale, and to provide a synchronization method.This synchronization circuit...  
JP2011147165A
To provide a semiconductor device equipped with a register control delay lock loop (DLL) capable of reducing current consumption caused by unnecessary toggling of DLL clock.The semiconductor device comprising an internal circuit that use...  
JP4734510B2
A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass fi...  
JP2011142503A
To provide a variable frequency dividing circuit which performs higher-speed frequency dividing operation.The variable frequency dividing circuit is provided with: a plurality of flip-flop circuits CT0-CT5 which receive a clock signal cl...  
JP4724506B2  

Matches 401 - 450 out of 4,634