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Matches 1 - 50 out of 6,250

Document Document Title
WO/2020/243414A1
Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in po...  
WO/2020/218954A1
A method performed by a first network entity (121, 131) for authenticating an event in a communications network (101, 102, 103, 104) is provided. The first network entity (121, 131) is configured to receive an event signal. The first net...  
WO/2020/211108A1
A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage out...  
WO/2020/166349A1
The present technology relates to a light receiving device, a histogram generation method, and a ranging system which enable a histogram generation circuit to be implemented with a small area and low power consumption. This light receivi...  
WO/2020/104414A1
A network participant (7) of an automation communication network (1) is provided in order to exchange data with additional network participants (2) in the automation communication network (1) at a defined clock frequency. The network par...  
WO/2020/086269A1
A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in...  
WO/2020/024515A1
A low-jitter frequency division clock circuit comprises: a clock control signal generation circuit, used to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, used to g...  
WO/2020/008229A1
The present disclosure relates to a fault detection circuit comprising: sampling elements (SE_1 to SE_L) configured to sample signals present at a plurality of nodes (n1 to nL) of an asynchronous circuit (100); a logic circuit (110) conf...  
WO/2019/239537A1
The present invention has: a first latch circuit (11) that has a pair of input transistors respectively having gates connected to a signal line having a first voltage supplied therethrough and has a pair of output nodes, and that has inp...  
WO/2019/137933A1
A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage del...  
WO/2019/137934A1
A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage del...  
WO/2018/089121A3
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/119188A3
Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network...  
WO/2018/119188A2
Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network...  
WO/2018/096973A1
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...  
WO/2018/094924A1
Disclosed in the embodiments of the present invention are a programmable frequency divider and a computer storage medium. The programmable frequency divider comprises: a state machine unit configured to control a state transition when an...  
WO/2017/177243A1
The invention relates to a code generator, in which a plurality of flip-flops (R1, R2, R3) is interconnected to form a circuit. In addition, feedback is provided, wherein an output (Q) and an input (D) of the flip-flops (R1, R2) are recu...  
WO/2017/158761A1
A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal outputted from a last-stage one of dual modulus frequency dividers, among a plurality of dual modulus frequency div...  
WO/2017/154191A1
A divider circuit includes: a first divider circuit unit (10) that generates a first divided clock signal by dividing a first clock signal; a second divider circuit unit (20) that generates a second divided clock signal by dividing a sec...  
WO/2017/121228A1
A method for keeping phases of frequency division clocks consistent and a frequency division circuit. The method comprises: connecting an input end D of a last-level register of a first frequency divider with an input end D of a last-lev...  
WO/2017/084217A1
An E-TSPC structure-based low-power-consumption 2/3 frequency divider circuit comprises a first-stage D trigger DFF1, a second-stage D trigger DFF2, and an inter-stage embedded gate circuit. A clock signal Clk serves as a clock signal to...  
WO/2017/048419A1
Systems and methods for dividing input clock signals (CLKin) by programmable divide ratios (N) can produce output clock signals (CLKdiv) with the delay from the input clock signal to the output clock signal independent of the value of th...  
WO/2016/202367A1
An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a ...  
WO/2016/089291A1
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...  
WO/2016/089292A1
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...  
WO/2016/089275A1
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...  
WO/2016/076798A1
A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the trans...  
WO/2015/136659A1
In a PLL circuit (1001), first of all, an output voltage (Vtune) of an LPF (50) is coupled to an ILFD (10(n)), whereby the ILFD (10(n)) becomes an oscillator. The ILFD (10(n)), a DIV (20), a PFD (30), a CP (40) and the LPF (50) form a PL...  
WO/2015/128015A1
The apparatus (1) for generating random bits (ZB) comprises a plurality of mapping devices (21 – 2m), wherein a respective mapping device (21 – 2m) is set up to map a prescribed number n of input signals (E11 - Emn) using a combinato...  
WO/2015/086826A1
The invention, which relates to an arrangement and method for converting a photocurrent, is based on the object of specifying a solution that is used to achieve a reduction in the area requirement for the arrangement by eliminating opera...  
WO/2015/079663A1
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, fro...  
WO/2015/065683A1
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...  
WO/2014/209717A3
A high-speed and low power divider (100) includes a ring of four dynamic latches (101-104), an interlocking circuit (110), and four output inverters (106-109). Each latch has a first dynamic node M and a second dynamic node N. The interl...  
WO/2014/169681A1
Disclosed is a multimode programmable frequency divider, comprising: cascaded 2/3 frequency dividing units, a real-time power consumption control circuit, and a power switch control transistor, wherein the number of the frequency dividin...  
WO/2014/062983A3
Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverter...  
WO/2014/092696A1
A shift register ring stores bits. A data operation may be performed in the shift register ring if bits in the shift register ring are in a home position  
WO/2014/062983A2
Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverter...  
WO/2012/058010A3
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges...  
WO/2014/017472A1
In the present invention, a clock signal generation device divides a reference clock signal and generates a clock signal having a target average frequency. More specifically, a reference clock signal is divided at a first dividing ratio ...  
WO/2014/006447A1
A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a stat...  
WO/2013/156822A1
The invention relates to a Frequency Divider Circuit (300) for dividing an input RF signal (312) to a frequency divided RF signal (316). The circuit comprises a RF pair (310), a switching-quad pair (306) coupled in series with a transimp...  
WO/2013/140755A1
An injection-locked frequency divider (ILFD) control unit (520) establishes a control parameter of an IFLD (303b) on the basis of the frequencies of a reference signal and of a frequency-divided signal measured in accordance with a contr...  
WO/2013/121149A1
According to this method, a carry generation command (M) is applied repetitively to a command input (G) of a carry-propagation logic circuit (1), the application of said command (M) to said input (G) is timed by means of a reference cloc...  
WO/2013/098127A1
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-...  
WO/2013/073268A1
A latch circuit (1) is equipped with: a PMOS transistor (10), the drain of which is connected to a first output node and the gate of which is connected to a second output node; a PMOS transistor (12), the drain of which is connected to t...  
WO/2013/062855A1
A mixed-signal radio frequency receiver implements multiple spur avoidance modes to reduce or remove spurs or digital noise injection into the received channel to enhance the receiver performance. The multiple spur avoidance modes are re...  
WO/2013/057060A1
A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an ...  
WO/2013/048525A1
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division...  
WO/2013/020900A1
A frequency divider (100) comprises a signal generation stage (110) arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first...  
WO/2013/012755A1
Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multip...  

Matches 1 - 50 out of 6,250