Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 1 - 50 out of 6,196

Document Document Title
WO/2017/177243A1
The invention relates to a code generator, in which a plurality of flip-flops (R1, R2, R3) is interconnected to form a circuit. In addition, feedback is provided, wherein an output (Q) and an input (D) of the flip-flops (R1, R2) are recu...  
WO/2017/158761A1
A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal outputted from a last-stage one of dual modulus frequency dividers, among a plurality of dual modulus frequency div...  
WO/2017/154191A1
A divider circuit includes: a first divider circuit unit (10) that generates a first divided clock signal by dividing a first clock signal; a second divider circuit unit (20) that generates a second divided clock signal by dividing a sec...  
WO/2017/121228A1
A method for keeping phases of frequency division clocks consistent and a frequency division circuit. The method comprises: connecting an input end D of a last-level register of a first frequency divider with an input end D of a last-lev...  
WO/2017/084217A1
An E-TSPC structure-based low-power-consumption 2/3 frequency divider circuit comprises a first-stage D trigger DFF1, a second-stage D trigger DFF2, and an inter-stage embedded gate circuit. A clock signal Clk serves as a clock signal to...  
WO/2017/048419A1
Systems and methods for dividing input clock signals (CLKin) by programmable divide ratios (N) can produce output clock signals (CLKdiv) with the delay from the input clock signal to the output clock signal independent of the value of th...  
WO/2016/202367A1
An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a ...  
WO/2016/089291A1
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...  
WO/2016/089292A1
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...  
WO/2016/089275A1
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...  
WO/2016/076798A1
A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the trans...  
WO/2015/136659A1
In a PLL circuit (1001), first of all, an output voltage (Vtune) of an LPF (50) is coupled to an ILFD (10(n)), whereby the ILFD (10(n)) becomes an oscillator. The ILFD (10(n)), a DIV (20), a PFD (30), a CP (40) and the LPF (50) form a PL...  
WO/2015/128015A1
The apparatus (1) for generating random bits (ZB) comprises a plurality of mapping devices (21 – 2m), wherein a respective mapping device (21 – 2m) is set up to map a prescribed number n of input signals (E11 - Emn) using a combinato...  
WO/2015/086826A1
The invention, which relates to an arrangement and method for converting a photocurrent, is based on the object of specifying a solution that is used to achieve a reduction in the area requirement for the arrangement by eliminating opera...  
WO/2015/079663A1
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, fro...  
WO/2015/065683A1
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...  
WO/2014/209717A3
A high-speed and low power divider (100) includes a ring of four dynamic latches (101-104), an interlocking circuit (110), and four output inverters (106-109). Each latch has a first dynamic node M and a second dynamic node N. The interl...  
WO/2014/169681A1
Disclosed is a multimode programmable frequency divider, comprising: cascaded 2/3 frequency dividing units, a real-time power consumption control circuit, and a power switch control transistor, wherein the number of the frequency dividin...  
WO/2014/092696A1
A shift register ring stores bits. A data operation may be performed in the shift register ring if bits in the shift register ring are in a home position  
WO/2014/062983A3
Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverter...  
WO/2014/062983A2
Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverter...  
WO/2014/017472A1
In the present invention, a clock signal generation device divides a reference clock signal and generates a clock signal having a target average frequency. More specifically, a reference clock signal is divided at a first dividing ratio ...  
WO/2014/006447A1
A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a stat...  
WO/2013/156822A1
The invention relates to a Frequency Divider Circuit (300) for dividing an input RF signal (312) to a frequency divided RF signal (316). The circuit comprises a RF pair (310), a switching-quad pair (306) coupled in series with a transimp...  
WO/2013/140755A1
An injection-locked frequency divider (ILFD) control unit (520) establishes a control parameter of an IFLD (303b) on the basis of the frequencies of a reference signal and of a frequency-divided signal measured in accordance with a contr...  
WO/2013/121149A1
According to this method, a carry generation command (M) is applied repetitively to a command input (G) of a carry-propagation logic circuit (1), the application of said command (M) to said input (G) is timed by means of a reference cloc...  
WO/2013/098127A1
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-...  
WO/2013/073268A1
A latch circuit (1) is equipped with: a PMOS transistor (10), the drain of which is connected to a first output node and the gate of which is connected to a second output node; a PMOS transistor (12), the drain of which is connected to t...  
WO/2013/062855A1
A mixed-signal radio frequency receiver implements multiple spur avoidance modes to reduce or remove spurs or digital noise injection into the received channel to enhance the receiver performance. The multiple spur avoidance modes are re...  
WO/2013/057060A1
A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an ...  
WO/2013/048525A1
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division...  
WO/2013/020900A1
A frequency divider (100) comprises a signal generation stage (110) arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first...  
WO/2013/012755A1
Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multip...  
WO/2013/009918A1
A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching betwee...  
WO/2013/000849A2
The invention relates to an electronic circuit especially comprising: a comparator (12) receiving a threshold potential (Vcomp) and the potential of an integration node (N), said node being able to store electrical charges generated by a...  
WO/2012/167686A1
Disclosed are a frequency division device and method. The device includes: a feedback control platform, a multiplexing frequency divider; the feedback control platform including a parameter setting module being set to set an initial valu...  
WO/2012/168533A1
An apparatus comprising a clock shaper (510) configured to derive a frequency of a reference clock signal (501) into a plurality of n frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1,..., Clock n-1 (571-0, 571-1,...  
WO/2012/161003A1
A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number o...  
WO/2012/150621A1
A frequency synthesizer according to the present invention is provided with a decimal part data output unit (10) which generates two values for decimal part data (F, F+1) and outputs either one of the generated two values by switching ba...  
WO/2012/131795A1
A CML clock division circuit (1A) according to the present invention is provided with a plurality of latch circuits (31, 32) having a first and a second transistor groups (301, 302) which receive clock signals (CLK1, NCLK1) at the gates ...  
WO/2012/129553A1
A frequency divider circuit is described. The frequency divider circuit (602) includes a first cross - coupling (606a). The first cross - coupling (606a) includes a first cross - coupled transistor (650a) with a first gate (608a). The fi...  
WO/2012/103090A1
A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly div...  
WO/2012/058010A3
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges...  
WO/2012/041852A3
An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successive...  
WO/2012/035941A1
The disclosed frequency divider circuit is provided with: a variable frequency divider (2) which frequency-divides a periodic signal (s5) with two frequency division ratios and outputs a first frequency-divided signal (c1); a counter cir...  
WO/2012/035800A1
A frequency division circuit according to the present invention comprises: a variable-frequency divider (2) that outputs a first frequency-divided signal (c1) obtained by frequency division of a periodic signal (s5) at two different freq...  
WO/2012/021511A3
A frequency divider (200) includes a least significant (LS) stage (220), multiple cascaded divider stages (230-1 to 230-N), and an output stage (210). The LS stage (220) receives an input signal (201), a program bit and a first mode sign...  
WO/2012/021511A2
A frequency divider (200) includes a least significant (LS) stage (220), multiple cascaded divider stages (230-1 to 230-N), and an output stage (210). The LS stage (220) receives an input signal (201), a program bit and a first mode sign...  
WO/2012/014060A1
A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input...  
WO/2011/156622A1
Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase base...  

Matches 1 - 50 out of 6,196