Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 1 - 50 out of 26,712

Document Document Title
WO/2020/018716A1
A communicate device includes transmitters and a receiver. The first transmitter is coupled to a first 90º phase shifter that is also coupled to a first antenna, and to a second 90º phase shifter that is also coupled to a first node. T...  
WO/2020/011801A1
The invention relates to a digital isolator comprising a logic module (20) for receiving an input signal D, and providing command signals (41, 42) to sawtooth modulators. A first sawtooth modulator STM1 provides a first sawtooth signal a...  
WO/2020/006649A1
A multi-bit flip flop (1). The multi-bit flip flop (1) comprises a clock input pin (PIN1), a clock buffer circuit (110), and multiple flip flops (121-128). The clock buffer circuit (110) is used for receiving a first clock signal (CP) fr...  
WO/2020/007979A1
The present application provides a level shifter in integrated circuit with a reduced N-well spacing requirement.  
WO/2020/006213A1
Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information dur...  
WO/2020/005438A1
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communi...  
WO/2020/001167A1
A dynamic D flip-flop (400, 500, 600) and a data operation unit (700) using same, a chip (800), a hash board (900) and a computing device (1000). The dynamic D flip-flop (400, 500, 600) comprises an input end (404), an output end (405) a...  
WO/2019/245901A1
Improvements in a battery optimization and restoration device that uses a means of varying the regulator voltage as a function of time and discharge event timing and depth in order to establish a consistent power level for the charging o...  
WO/2019/245902A1
Improvements in a battery optimization and restoration device that uses a means of varying the regulator voltage as a function of time and discharge event timing and depth in order to establish a consistent power level for the charging o...  
WO/2019/237733A1
A narrow pulse generation circuit used in a sequential equivalent sampling system. The circuit comprises a crystal oscillator, an edge sharpening circuit, an avalanche transistor single-tube amplifying circuit and a shaping network conne...  
WO/2019/236224A1
Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a first passgate, a first latch, a second passgate, and a second latch. The first latch may include a first inverter and a first logic gate. The...  
WO/2019/237114A1
Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits havin...  
WO/2019/235363A1
A D-type flip-flop circuit 1 has a configuration in which a pMOS transistor p8 and an nMOS transistor n8 are added to pMOS transistors p1-p7, p11-p15 and nMOS transistors n1-n7, n11-n15 which are provided to a typical D-type flip-flop ci...  
WO/2019/229593A1
Provided is a semiconductor device wherein calculation accuracy has been increased due to correction of a threshold value voltage. This semiconductor device has first and second current source circuits, wherein the second current source ...  
WO/2019/224819A1
A device and method are disclosed for regulated storage capacitor charging to high voltage. The device comprises an AC source configured to output an AC voltage, a voltage multiplier that constitutes a charging unit and a control unit. T...  
WO/2019/226256A1
In certain aspects of the disclosure, an apparatus (100) comprises a latching element (110) having a data input (118b), a first feedback input (118a), a second feedback input (118c), and an output (140). A pull-up input block (122) is co...  
WO/2019/222695A1
A crystal-free wireless device includes a frequency calibration module and a local radio frequency (RF) oscillator having a first frequency and configured to communicate with the frequency calibration module. The crystal-free wireless de...  
WO/2019/220123A1
An AND gate comprises:a first input;a second input;an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may...  
WO/2019/220839A1
This semiconductor device comprises: a ring oscillator that includes a plurality of gate circuits disposed on a circuit path and having a first gate circuit, and that includes a first load circuit having a first capacitance element which...  
WO/2019/220193A1
Random number generator (GL) comprises three ring oscillators (GP1, GP2, GP3) and seven bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7). The ring oscillators (GP1, GP2, GP3) comprise delay lines (LO1, LO2, LO3) closed in loops. The delay l...  
WO/2019/217153A1
One example includes a current driver system. The system includes a current source configured to provide a source current to a transition node. The system also includes a Josephson latch comprising at least one Josephson junction stage. ...  
WO/2019/217836A1
Systems and methods for activation in an optical circuit in accordance with embodiments of the invention are illustrated. One embodiment includes an optical activation circuit, wherein the circuit comprises a directional coupler, an opti...  
WO/2019/211979A1
The present invention reduces jitter superimposed on a clock signal. This clock generation circuit is provided with: a mode-locked laser 1 that generates an optical pulse; a photodiode 2 that performs photoelectric conversion of the opti...  
WO/2019/211099A1
The invention relates to an actuation circuit (50) for a pulsating actuation of a lighting means (52), in particular an LED or a laser diode (52), comprising: a switched-mode power supply (54) comprising a first switch (64) which is arra...  
WO/2019/207093A1
The invention is referred to an electronic assembly (1) for an automotive lighting device (10). This electronic assembly (1) comprises a first pattern generation unit (3), arranged in direct electric contact with the input (2), a first s...  
WO/2019/209556A1
A system for determining characteristics of a specific region within an inhomogeneous dielectric specimen by guiding propagation of electric fields through the inhomogeneous dielectric specimen is provided herein. Various embodiments inc...  
WO/2019/203937A1
In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resist...  
WO/2019/201805A1
The invention relates to a method for generating a short light pulse and to a light source (1) for generating light pulses with a short pulse duration, in particular for use in a vehicle, said light source comprising a light-emitting dio...  
WO/2019/203968A1
Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuity into the signal being transmitted...  
WO/2019/195507A1
According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay ele...  
WO/2019/192991A1
The invention relates to a device (10) and a corresponding method (40) for providing a high-resolution PWM signal. The device (10) comprises: an energy store (21A; 21B); a power source (22A; 22B); switching means (11, 12), which is desig...  
WO/2019/184395A1
A flip-flop (700) and an integrated circuit, wherein same are used to reduce the probability of the occurrence of the phenomenon of metastability of a flip-flop. The flip-flop (700) comprises: a first latch (701), a second latch (702), a...  
WO/2019/190810A1
Superconducting integrated circuits with clock signals distributed via an inductive coupling and related methods are provided. A method includes providing a D flip-flop having a clock terminal coupled to receive clock pulses from a clock...  
WO/2019/182697A1
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more...  
WO/2019/180744A1
Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration tec...  
WO/2019/171937A1
Provided is a semiconductor integrated circuit device that comprises a flip-flop circuit using vertical nanowire FET (VNW FET) and has a layout structure for minimizing area. A latch unit (30) of the flip-flop circuit comprises: a feedba...  
WO/2019/173821A1
A circuit includes a time-to-digital converter (TDC) (102) to produce an output signal that is a function of a time difference between a first input clock to the TDC (102) and a second input clock to the TDC (102). A first delay line (50...  
WO/2019/097532A9  
WO/2019/173021A1
An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry ...  
WO/2019/168708A1
Systems and methods are provided for linking two components in a superconducting circuit. A plurality of circuit elements, each comprising one of an inductor, a capacitor, and a Josephson junction, are connected in series on a path conne...  
WO/2019/168983A1
A clock divider (200) includes a clock delay line (210), delay elements (250), a clock delay selector (220) coupled to the clock delay line (210) and configured to select one of the delay elements (250), and a bit pattern source (230, 24...  
WO/2019/167353A1
This voltage control oscillator with a high power-supply voltage variation removal ratio and this voltage current conversion circuit of the voltage control oscillator make it possible to have low voltage operations. A cascode-connected t...  
WO/2019/154611A1
The technology is generally directed towards a pulse generation component that outputs a control pulse with a timing delay. A qubit state decision component uses an analog kernel to perform a linear filtering operation on (e.g., multipli...  
WO/2019/152282A1
A reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with ...  
WO/2019/152281A1
A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provi...  
WO/2019/145309A1
The invention relates to a circuit arrangement (1) for generating cyclically successive current impulses (I1, ... In) on contacts (K1, K2), which are to be cleaned, of a target value monitor, which, for continual querying of a target val...  
WO/2019/145753A1
The present invention concerns an electronic device (1000) comprising a digital circuit (6) to be compensated and a compensation device for compensating PVT variations of this digital circuit (6). This compensation device is arranged als...  
WO/2019/142203A1
Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse ge...  
WO/2019/142546A1
This semiconductor integrated circuit is provided with: a first flip-flop (1a) provided with a first slave latch; a second flip-flop (2a) provided with a second slave latch; and a clock generation circuit (3) that supplies a common clock...  
WO/2019/143302A1
According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrical...  

Matches 1 - 50 out of 26,712