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WO/2017/151295A1 |
An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having...
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WO/2017/147895A1 |
In one example, an apparatus may be a flip-flop that includes a slave latch and a master latch. The master latch includes a first logic element in the master latch. The first logic element includes a first transistor. The first transisto...
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WO/2017/151301A1 |
A method of generating a bandgap voltage in an electronic circuit includes generating a bandgap current. The method further includes operating the electronic circuit using the bandgap voltage and the bandgap current. The operating can be...
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WO/2017/149978A1 |
[Problem] To provide a ring oscillator capable of controlling frequency according to the delay amount of a delay element, with a structure for which fine-level frequency setting is possible. [Solution] A reference signal generation devic...
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WO/2017/151261A1 |
A sub-microsecond pulsed electric field generator is disclosed. The field generator includes a controller, which generates a power supply control signal and generates a pulse generator control signal, and a power supply, which receives t...
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WO/2017/151293A1 |
In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first ...
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WO/2017/146650A1 |
Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third...
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WO/2017/143573A1 |
A pulse generating device, belonging to the field of distance measurement, comprising: a level generating module (01), a level conversion module (02), and a pulse generating module (03); the level generating module (01) generating, accor...
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WO/2017/144855A1 |
According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron switch, hereinafter termed CES, element. The latching circuitry furth...
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WO/2017/142664A1 |
Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multip...
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WO/2017/142696A1 |
The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The firs...
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WO/2017/133466A1 |
A high-speed low-power-consumption trigger, comprising a control signal generating circuit, an enabling unit and a latch structure, wherein the latch structure includes two input terminals, two output terminals, two enabling terminals, a...
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WO/2017/128647A1 |
A trigger and an oscillation system. The trigger comprises: a first voltage input end (1); a bias voltage input end (2); a first offset pipe (M5), which is configured with a scaling ratio relative to a first component of an external appa...
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WO/2017/129947A1 |
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage (212), a resistor (Rl), a capacitor (CI), and active switches (Ml, M2) arranged to provide a clock sign...
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WO/2017/124094A1 |
An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs...
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WO/2017/120002A1 |
A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal (320) in a first power domain (302) and initiate a second clock signal (3...
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WO/2017/118873A2 |
Layouts of transmission gates and related techniques and systems are described. An integrated circuit may include first and second transmission gates disposed in a column, and metal wires. The first transmission gate includes first and s...
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WO/2017/120244A1 |
A signal generator configured to generate an oscillating signal with a temperature-compensated frequency. The signal generator includes a ring oscillator, and a complementary to absolute temperature (CTAT) current generator configured to...
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WO/2017/096376A1 |
In described examples of control logic (12) for producing a digital input (DV) to a digital-to-analog converter (DAC) (14) in a power converter system (20), the control logic (12) selects from among a plurality of slew rates during a tra...
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WO/2017/087089A1 |
One embodiment describes a Josephson current source system (14). The system includes a flux-shuttle loop (16) comprising a plurality of stages arranged in a series loop. Each of the plurality of stages includes at least one Josephson jun...
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WO/2017/087070A1 |
One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages (14) that are arranged in series. The system also includes a clock transformer (12) comprising a primary inductor configur...
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WO/2017/079704A1 |
Implementations of light filters for use in cryptographic operations may include: a substrate having at least a first side and a second side, the first side opposing the second side, the substrate including one of a translucent, a transp...
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WO/2017/069857A1 |
Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type T...
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WO/2017/069985A1 |
A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal (D), a clock...
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WO/2017/069914A1 |
A method and an apparatus for wireless communication are provided. The apparatus having a first latch having a first latch input and first latch output and a second latch having a second latch input, a second latch scan output, and a sec...
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WO/2017/069843A1 |
An apparatus comprises a photonic oscillator circuit configured to generate optical signals that are separated by a uniform delay; radio frequency (RF) generating circuitry configured to receive the optical signals and produce a series o...
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WO/2017/054073A1 |
A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element,...
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WO/2017/052928A1 |
Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rai...
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WO/2017/052838A1 |
An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail (KPR), a collapsible power rail (CPR), multiple flip-flops (206), an...
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WO/2017/052733A1 |
An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.
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WO/2017/050999A1 |
The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output si...
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WO/2017/053019A1 |
A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillat...
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WO/2017/048550A1 |
Level shifter (200) includes latch circuit having first and second FETs (P1, P2); an input circuit having a third FET (N1) and a fourth FET (N2), the gates of the first and second FETs being coupled to the drains of the fourth and third ...
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WO/2017/039856A1 |
A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current ...
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WO/2017/033962A1 |
According to the present invention, an adder (12) adds a noise signal (SNS), an input signal (SI1), and a feedback signal (S4). A threshold determination unit (13) compares an addition signal (S1) outputted from the adder (12) with a pre...
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WO/2017/031575A1 |
An optoelectronic oscillator (OEO) is disclosed comprising an electronically tunable filter for transposing narrow pass band characteristics of a surface acoustic wave (SAW) filter to a microwave frequency to provide mode selection in th...
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WO/2017/030828A1 |
Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit (100) includes...
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WO/2017/030726A1 |
An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a sec...
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WO/2017/027157A1 |
A particular apparatus (100) includes a magnetic tunnel junction (MTJ) device (102) and a transistor (120). The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition...
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WO/2017/023294A1 |
A digital excitation signal generator can be used to modulate excitation current or voltage to be injected into a subterranean formation by a downhole logging tool. The digital excitation signal generator can include a processor and a pu...
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WO/2017/018930A1 |
The invention relates to a system for applying a superimposed time-varying frequency electromagnetic wave to a target object or a target region that is formed by the target object and a medium surrounding the target object, comprising a ...
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WO/2017/014368A1 |
A pulse power device is disclosed. The pulse power device according to a preferred embodiment of the present invention connects in parallel, to both ends of a semiconductor switch unit and an energy storage unit connected in series, a by...
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WO/2016/209588A1 |
Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to...
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WO/2016/210276A1 |
Method and apparatus to produce a step function with a designed transition (rise and/or fall) time on the order of <10ns that reaches steady state by implementing a system that sums a number of currents at different rise times (frequenci...
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WO/2016/209387A1 |
One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion assoc...
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WO/2016/200468A1 |
A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IĈ, and t...
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WO/2016/199522A1 |
A signal transmission circuit is provided with: first and second lines L1, L2 to which signals complementary to each other are inputted; first and second buffer circuits BA11, BA21; a first inverter BA12 which connects a first input-side...
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WO/2016/197107A1 |
In described examples, a decision feedback equalizer (DFE) (100) includes a first summing node (112), a first synchronization latch (114), a second synchronization latch (116), a first feedback latch (118), and a first feedback shift reg...
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WO/2016/195952A1 |
Voltage level shifters (100) employing preconditioning circuits (102) are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter (100) is configured to generate a voltage level shifted non-complem...
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WO/2016/197153A1 |
A fast latched comparator may include an amplifier portion and a latch portion. A switch activated by a reset pulse may short together outputs of the latched comparator.
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