| Document |
Document Title |
|
WO/2016/190956A1 |
A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first la...
|
|
WO/2016/191385A1 |
A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a fir...
|
|
WO/2016/189070A1 |
Method for generating a value (19) inherent to an electronic circuit (10) by means of measures of a physical quantity carried out on components (11) of this circuit; this method is intended to: calculate and associate to each component (...
|
|
WO/2016/187893A1 |
A multi-phase clock generating clock (51) and a liquid crystal display panel. The circuit (51) comprises a shifting register (13), which comprises N shifting register units (14) in mutual cascading, a first output end of an n-stage shift...
|
|
WO/2016/190255A1 |
A pulse generation device 10 is provided with: a substrate 24; a spin injector 14 disposed on the substrate 24 and comprising a ferromagnetic material; a spin rotor 18 disposed on the substrate 24 and comprising a ferromagnetic material,...
|
|
WO/2016/191383A1 |
A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a diff...
|
|
WO/2016/187333A1 |
Systems and techniques are provided for a multichannel waveform synthesis engine. A phase counter module counts to a value corresponding to a number of phases available, outputs a phase counter value indicating a current phase, and reset...
|
|
WO/2016/187479A1 |
A circuit for a divider or counter may include a frequency divider (200) having multiple rings (210, 220, 230) for dividing an input frequency (Vin, 202) to obtain an output frequency. The first and second rings (210, 220) may include an...
|
|
WO/2016/187358A1 |
The present application teaches configurations in which the multiple-ON-mode bidirectional bipolar switch is used to provide very simple circuit configurations which can - when requirements are not stringent - perform certain electrical ...
|
|
WO/2016/185903A1 |
The present feature relates to a small non-volatile storage circuit allowing power consumption to be reduced while maintaining stable write-in. An NVDFF is provided with a slave latch, the slave latch having a magnetoresistive element co...
|
|
WO/2016/182690A1 |
A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module (608), a first bias signal for a PMOS biasing module (604) based o...
|
|
WO/2016/182676A1 |
Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal (410) produced by a first ring oscillator ...
|
|
WO/2016/178742A1 |
Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay g...
|
|
WO/2016/178822A1 |
A microwave circuit (50) is provided that comprises a plurality of transmission lines (60) each configured to receive and propagate a respective waveform signal of a plurality of waveform signals, and a combiner (58) that receives and co...
|
|
WO/2016/174384A1 |
A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in re...
|
|
WO/2016/176412A1 |
A high voltage capacitive load driver circuit includes a supply voltage, a first capacitor connected across a first node and a common node, a second capacitor connected across a second node and the common node, two drivers each having a ...
|
|
WO/2016/169746A1 |
A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to ...
|
|
WO/2016/171582A1 |
The invention relates to pulse technology. A generator includes a diode which is capable of fast recovery and which is connected to ground, a switch, first and second capacitors, and first and second inductors, forming a resonant circ...
|
|
WO/2016/167818A1 |
A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node cou...
|
|
WO/2016/160236A1 |
A latch-based level-shifter is provided that includes an edge-triggered pulse generator (110) that drives a switch (115) to switch off and isolate a pair of cross-coupled inverters (105) in the level-shifter from ground for a transition ...
|
|
WO/2016/158691A1 |
This electronic circuit is provided with: a bistable circuit which is connected between a positive power source to which a power source voltage is supplied, and a negative power source, and in which a first inverter and a second inverter...
|
|
WO/2016/161134A1 |
Described herein is a combination of mixed-signal hardware and software that is capable or realizing hybrid chaotic oscillators that can be tuned digitally. This includes the type/class of chaotic oscillator, initial conditions, nonlinea...
|
|
WO/2016/146635A1 |
High-voltage pulse generator comprising a plurality of stages and an electrode (ELR) for returning current to earth, connected in series, each of the stages comprising at least one energy storage element (C1, C2, C3, C4) connected in ser...
|
|
WO/2016/140745A1 |
Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state retention flip-flop having a plurality of P-type metal oxide semiconductor (PMOS) devi...
|
|
WO/2016/134605A1 |
A comparator (134) comprises a differential input stage (139) comprising a first n-type transistor (M1) and a second n-type transistor (M2), an output stage coupled to the differential input stage (139), a clock transistor (M10) coupled ...
|
|
WO/2016/136448A1 |
The present disclosure relates to a comparator, an AD converter, a solid-state imaging apparatus, an electronic device, a comparator control method, a data writing circuit, a data reading circuit, and a data transferring circuit that all...
|
|
WO/2016/133394A1 |
A qubit system is provided wherein successive sets of M RF pulses are generated simultaneously, for application to qubit circuits in a plurality of N groups of M qubit circuits. M switching multiplexer circuits are used, each to pass a r...
|
|
WO/2016/129149A1 |
Provided is a register circuit the initial value of which is changeable without using a flip-flop having both a set terminal and a reset terminal. The register circuit is provided with: a first flip-flop that changes a first signal from ...
|
|
WO/2016/130044A1 |
The group of inventions relates to pulse technology. The generator comprises the following, connected consecutively: an inductive energy accumulator and a drift diode with fast back-resistance recovery, and also a load which is connec...
|
|
WO/2016/130290A1 |
A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops an...
|
|
WO/2016/108989A1 |
A transition tracking circuit (106) may be configured to receive a first input signal (VA) and a second input signal (VAB) from a level shifter (102). The transition tracking circuit (106) may be configured to track earlier falling trans...
|
|
WO/2016/103929A1 |
The purpose of the present invention is to improve maintenance operations by changing the output time of a warning alarm in response to an overheated state. A semiconductor device (1-1) is provided with a semiconductor switch (1a) and a ...
|
|
WO/2016/106429A1 |
In described examples, a universal oscillator (200) includes an amplifier array (204) that includes one or more amplifiers. A control logic unit (220) is coupled to the amplifier array (204) and activates the one or more amplifiers. A se...
|
|
WO/2016/103845A1 |
In the present invention, a signal detector is equipped with an input signal amplifying circuit, a reference signal amplifying circuit, and a comparator in order to accurately detect the presence of a signal. The input signal amplifying ...
|
|
WO/2016/097699A1 |
A relaxation oscillator (2) comprises: a comparator (4) comprising: a differential pair of transistors (140, 142, 144. 40, 42, 44); a static current source (32); and a dynamic current source (32); and at least one energy storage componen...
|
|
WO/2016/100449A1 |
Apparatus and methods for temperature compensation of variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array, an array biasing circuit that biases cells of the v...
|
|
WO/2016/093891A1 |
An apparatus (100, 700) includes a first programmable circuit block (102, 106) including a plurality of programmable circuit elements. The plurality of programmable circuit elements include a hardwired, instrumented memory element (200)....
|
|
WO/2016/089291A1 |
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...
|
|
WO/2016/089292A1 |
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...
|
|
WO/2016/089260A1 |
The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further compr...
|
|
WO/2016/089275A1 |
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...
|
|
WO/2016/081138A1 |
A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.
|
|
WO/2016/077200A1 |
An asymmetric hysteretic controller comprises an analog comparator coupled with a fast slew rate DAC, or a digital comparator coupled with an ADC plus some digital control logic. The comparator, analog or digital, operates as a sequentia...
|
|
WO/2016/073121A2 |
Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down ...
|
|
WO/2016/073119A1 |
A driver circuit includes an output driver (308) including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster (316) configured to adjust a duty cycle of a signal provided to the output driver. Th...
|
|
WO/2016/068910A1 |
A method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis ...
|
|
WO/2016/068520A2 |
The present invention relates to an electronic vibrator comprising: a power supply unit for converting AC power into DC power; a bridge circuit unit comprising an IGBT, as a power switching element, in order to enable driving of a large-...
|
|
WO/2016/064492A1 |
An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The conver...
|
|
WO/2016/055913A1 |
A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the f...
|
|
WO/2016/057088A1 |
A circuit for providing voltage level shifting in an integrated circuit includes an inverter (610) having an input coupled to receive an input signal having a first voltage level (VDDL); an output stage (618) having a first transistor (6...
|
