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Patent Searching and Data


Matches 651 - 700 out of 26,717

Document Document Title
WO/2011/068928A1
A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock s...  
WO/2011/063974A1
It is described a driving circuit (1) having at least one output terminal (OUT) connected to an ultrasonic pulse generator circuit and providing thereto with an output voltage (Vout), characterized in that it comprises at least one first...  
WO/2011/065685A2
The present invention relates to an oscillator circuit which compensates for external supply voltage, temperature and process, and comprises: an external supply voltage (VDD) and a reference voltage generating unit (310) which generates ...  
WO/2011/062075A1
To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically ...  
WO/2011/063119A1
Embodiments relate to methods and devices comprising an optical pipe comprising a core and a cladding. An embodiment includes obtaining a substrate comprising a photodiode and a first protective layer, the first protective layer having a...  
WO/2011/055103A1
A clock arrangement to provide clock signals in an integrated circuit are disclosed. The clock arrangement comprises a conductive signal path formed as a non-inverting closed loop (10), a drive circuit (30) for generating phase-shifted o...  
WO/2011/031190A3
The invention pertains to the field of electrical engineering, more specifically to techniques and equipment for accumulating electrical energy in large amounts with low weight-dimension indices. The technical result consists in the prod...  
WO/2011/031188A3
The invention relates to the field of electrical engineering, in particular to technology and equipment for transmitting electrical energy via a single conducting channel. The technical result consists in reducing energy transmission los...  
WO/2011/052383A1
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal...  
WO/2011/047861A1
Ring oscillator comprising a plurality of elementary units (5) connected in cascade and linked in order to make a chain with the respective output terminals (OUT) connected to the input terminals (IN) of the successive elementary units (...  
WO/2011/045280A1
The invention relates to an oscillator, and to a method for generating electric oscillations depending on a frequency control signal having a transfer oscillator circuit for generating the electric oscillations and a control loop for reg...  
WO/2010/142708A3
The invention concerns a device for actuating a laser diode (230) and comprises an electrical circuit used for generating a pulsed output signal and to which a preset trigger pulse (239) can be applied. The pulse form is determined by a ...  
WO/2010/096832A3
An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a c...  
WO/2011/038788A1
The present invention relates to a method of generating a hole or recess or well in an electrically insulating or semiconducting substrate, and to a hole or recess or well in a substrate generated by this method. The invention also relat...  
WO/2011/039846A1
Disclosed is a random number generation circuit which generates random numbers. The random number generation circuit is provided with: an oscillation circuit having an amplifier row, which has a plurality of amplifiers connected in serie...  
WO/2011/036212A1
The present invention relates to a static frequency divider circuitry comprising a delay flip-flop related structure. An object of the present invention is to design a frequency divider circuitry that meets upcoming low power requirement...  
WO/2011/011639A3
Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter (102) inc...  
WO/2011/034862A1
A latching element (124) latches incoming data (D(7:0)) into an integrated circuit (101). The latching element (for example, a latch or flip-flop) can be considered to include a data path portion (126), a clock path portion (127), and an...  
WO/2011/031190A2
The invention pertains to the field of electrical engineering, and particularly relates to techniques and equipment for accumulating electrical energy in large amounts with low weight-dimension indices. The technical result consists in t...  
WO/2011/032149A2
A high-voltage bipolar rectangular pulse generator using a high efficiency solid-state boosting front-end and an H-bridge output stage is described. The topology of the circuit generates rectangular pulses with fast rise time and allows ...  
WO/2011/010146A3
The present invention provides a real-time clock circuit (54), comprising: an oscillator (122); and a counter (124), coupled to an output of the oscillator (122), for generating a real-time clock value. In a first mode the oscillator (12...  
WO/2011/030780A1
This invention provides a latch circuit that, even when connected to a CML buffer in the following stage, can operate at a high speed. There are included first and second input terminals; an output terminal; a driver circuit that, when t...  
WO/2011/031188A2
The invention relates to the field of electrical engineering, in particular to technology and equipment for transmitting electrical energy via a single conducting channel. The technical result consists in reducing energy transmission los...  
WO/2011/027553A1
An aging diagnostic device has a reference-use ring oscillator (101) constituted by a ring oscillator using a odd-numbered plurality of logic gates constituted using CMOS circuits; a test-use ring oscillator (102) constituted by a ring o...  
WO/2011/020436A1
A frequency jittering circuit and a method for generating frequency jitter. The frequency jittering circuit(100) comprises: an oscillating circuit(101) which generates an oscillation frequency output signal(201); a decoding circuit(102),...  
WO/2011/022005A1
A ring oscillator is disclosed for generating one or more clock signals. In some embodiments, the ring oscillator includes a first set of n series coupled inverters, a second set of n series coupled inverters, a first reset switch config...  
WO/2011/018818A1
A differential SR flip-flop (100) generates a differential output pair (Q, #Q) upon receiving a set signal (S) and a reset signal (R). A first flip-flop (FF1) generates a noninverted output (Q1) and an inverted output (#Q1). A second f...  
WO/2011/011639A2
Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes ...  
WO/2011/007944A1
Disclosed is a feed-forward ring oscillator. The feed-forward ring oscillator according to the present invention comprises of: a plurality of delay cells for outputting differential output signal couples by receiving first differential i...  
WO/2011/002337A1
The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), ...  
WO/2011/003101A1
A high frequency divider (124) involves a plurality of differential latches (142,143). Each latch includes a pair of cross-coupled P-channel transistors (158,159 and 161,162) and a variable resistance element (163,164). The latch is cont...  
WO/2011/001785A1
Provided is a semiconductor memory circuit having an extremely short set-up/hold time. The circuit is provided with a switch unit (SWBK1) which selects and outputs either a data input signal (Din_P, Din_N) or a reference potential line (...  
WO/2010/150607A1
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate dri...  
WO/2010/104556A3
A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, an...  
WO/2010/151891A2
Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a seco...  
WO/2010/145308A1
A power control device is provided. The device includes an adapter power supply signal generation unit for generating an adapter power supply signal according to an output voltage of an adapter; a switching on/off signal generation unit ...  
WO/2010/146756A1
Disclosed is a flip-flop provided with a first CMOS circuit in which the gate terminals and drain terminals of a P channel first transistor and an N channel second transistor are connected, a second CMOS circuit in which the gate termina...  
WO/2010/146843A1
Disclosed is a flip-flop, provided with a plurality of latch circuits with differing resistance to soft errors, and a clock distribution unit which feeds a clock to the plurality of latch circuits, wherein the plurality of latch circuits...  
WO/2010/135228A2
Techniques for providing a comparator incorporating amplitude hysteresis. In an exemplary embodiment, a current offset stage is coupled to a comparator having a folded cascode architecture. The current offset stage offsets the current ge...  
WO/2010/134257A1
Disclosed is a CMOS inverter type frequency divider with further reduced power consumption compared with the past. The CMOS inverter type frequency divider is provided with a plurality of CMOS inverters, a frequency division control unit...  
WO/2010/134197A1
This invention makes it possible to implement ECC functionality on a small surface area, and to prevent as much as possible the addition of unnecessary overhead. The invention is characterized by comprising: a physical random number gene...  
WO/2010/131076A1
A device (10, 11) that includes a dual edge triggered flip-flop (100, 101) that has state retention capabilities, the dual edge triggered flip-flop (100, 101) includes: a retention latch (110) that includes a first inverter (114), a seco...  
WO/2010/086642A3
A voltage level shifter has a supply voltage coupling to couple to a supply voltage having a reset voltage level and a programming voltage level, a control voltage input to couple to a control voltage having first and second voltage leve...  
WO/2010/126487A1
In a voltage-controlled ring oscillator, one or more controllable current sources generate a bias current in response to a tuning voltage. Any of several features can be included to promote frequency tuning linearity. In accordance with ...  
WO/2010/113108A1
A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator (33) configured to generate an output signal (F0) having a frequency controlled by an input digit...  
WO/2010/058401A3
A system for producing a high intensity electric current pulse is described. The system includes a plurality of discharge modules connected in parallel to a load device. Each discharge module comprises a capacitor bank and a high current...  
WO/2010/111857A1
A method and a body potential modulation circuit with anti process variation in the subthreshold integrated circuit are disclosed. The body potential modulation circuit includes an object MOS device (11), an induction MOS device (12) and...  
WO/2010/074976A3
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply v...  
WO/2010/115152A1
Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock ...  
WO/2010/108524A1
The invention relates to a circuit arrangement (1) for supplying a high-power functional component (20, 21) with high-voltage pulses, having: - two input connections (E1, E2) for application of an input voltage (UE), - two output connect...  

Matches 651 - 700 out of 26,717