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Patent Searching and Data


Matches 701 - 750 out of 26,704

Document Document Title
WO/2010/108810A1
A storage cell (1) having a pulse generator (5) and a storage element (6) is proposed. The storage element input (7) is connected to receive a data input signal (DIN). The storage element output (9) is connected to provide a data output ...  
WO/2010/108523A1
The invention concerns a high frequency generator for the connection of an electrosurgical instrument comprising an electrical output terminal for an electrosurgical instrument, a current or voltage source connected at least indirectly t...  
WO2010109793A1
A multi-screw chaotic oscillator circuit with a simple configuration, which can use a variety of multi-hysteresis VCCS characteristics, and which can generate a variety of multi-screw attractors. The multi-screw chaotic oscillator circui...  
WO/2010/108032A1
An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error ampl...  
WO/2010/106512A1
A voltage reference connects to a voltage-to-current converter to generate a reference current dependent on the reference voltage. Outputs of a toggle-type flip flop connect to switching transistors controlling the reference current char...  
WO/2010/104809A1
A bipolar pulse generator is implemented in a simple structure while providing a high efficiency design having a relatively low total size, while still allowing access by fibers used to control a photoconductive switch that activates the...  
WO/2010/104556A2
A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, an...  
WO/2010/099842A1
The present invention relates to a controlled truncating radio connection for a high-voltage impulse test system, preferably for quality assurance of power transformers. According to the invention, the truncating radio connection is expa...  
WO/2010/098202A1
A resistor (16) is provided between an input terminal and a node (N0). A switch (15) is provided between the node (N0) and a ground voltage (GND) and closes according to the voltage level of the node (NC). A resistor (13) is provided bet...  
WO/2010/099046A1
Methods and apparatus are described that develop a reference voltage that is based on a difference between a threshold voltage of a first transistor and a threshold voltage of a second transistor, and further based on a difference betwee...  
WO/2010/076556A3
The application relates to a conductivity measurement cell for measuring the concentration of a preselected biomarker or analyte in a body fluid, such as urine. In order to reduce the effect of sample dilution on measured concentration, ...  
WO/2010/096832A2
An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a c...  
WO/2010/089983A1
Disclosed is a multi-hysteresis voltage controlled current source system that has diverse multi-hysteresis characteristics. A multi-hysteresis voltage controlled current source system is configured with binary hysteresis voltage controll...  
WO/2010/091063A1
A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In ...  
WO/2010/087271A1
Provided is a nonvolatile logic circuit with a small surface area and which utilizes magnetoresistive elements. A nonvolatile latch circuit is provided with multiple serially connected magnetoresistive elements and a wire which is connec...  
WO/2010/083920A1
A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to com...  
WO/2010/068873A3
A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a sig...  
WO/2010/083628A1
A method for generating an actuation signal for a light source is provided. A random phase delay for each period of an input signal is generated, where each period is a predetermined length. Each phase delay is added to a predetermined a...  
WO/2010/077233A1
A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative...  
WO/2010/073458A1
A delay setting data generation unit (10) generates delay setting data DDS in accordance with rate data DRATE. A variable delay circuit (30) delays test pattern data DPAT by a delay time τ based on the delay setting data DDS with respe...  
WO/2010/073213A2
The invention relates to a device for compensating influence of temperature on a resonator circuit. The device comprises a resonator circuit and a supply unit for supplying an electric bias signal to the resonator circuit, wherein the su...  
WO/2010/074617A1
The present invention relates to a solution for electrical power conversion using a first gate (202, 302) for starting an electrical wave in a wave propagating medium (205, 306) acting as a transmission delay where an electrical wave pro...  
WO/2010/074976A2
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply v...  
WO/2010/071660A1
A level shifting circuit (104) includes a first stage (200) and a second stage (202). The first stage and second stage are operatively coupled to a first (110) and second (114) power supply. The first stage translates a differential inpu...  
WO/2010/070892A1
An oscillation circuit comprises an oscillator, further comprising a resonance frequency, an amplifier that is connected to the oscillator, an energized pulse emission unit, which emits a pulse of a frequency, from among the resonance fr...  
WO/2010/068873A2
A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a sig...  
WO/2010/066644A1
The invention provides a spark generator for generating a spark for optical emission spectroscopy (OES), wherein the spark has a current waveform comprising a first modulated portion which comprises a plurality of relatively high current...  
WO/2010/064888A1
There is disclosed a frequency divider, comprising: a clock input (CLK) adapted to receive a clock signal; a reset input (RST) adapted to receive a reset signal; a division circuit (30, 40) adapted to divide the clock signal by a factor ...  
WO/2010/027915A3
A level shifting circuit (402) has a pair of assist circuits (404, 40S). The level shifting circuit (402) includes an input point (420), two output points (416/418), a pair of cross-coupled PMOS transistors (412, 414) coupled to the outp...  
WO/2010/062550A1
A virtual ground restoration circuit (200) is used to substantially eliminate excessive current from occurring in an integrated circuit (102) device having two or more logic circuit modules (110,104) in different voltage domains. Excessi...  
WO/2010/059359A1
A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitr...  
WO/2010/058401A2
A system for producing a high intensity electric current pulse is described. The system includes a plurality of discharge modules connected in parallel to a load device. Each discharge module comprises a capacitor bank and a high current...  
WO/2010/057721A1
The invention pertains to the general field of tomography atomic probes, and more particularly to tomography atomic probes that use electric pulses applied to an electrode for vaporising the analysed sample. In order to generate the elec...  
WO/2010/058249A1
An integrated circuit (200, 800) comprising oscillator circuitry (210, 810) is arranged to generate a clock signal (230, 830) for functional logic module (220, 820) of the integrated circuit (200, 800). The oscillator circuitry (210, 810...  
WO/2010/056138A1
A method of operating an electric fence energiser, including the steps of:storing energy in an energy storage element, and transferring energy from the energy storage element to an inductive element, the method characterised by the steps...  
WO/2010/053215A1
An RTWO apparatus includes an N-phase RTWO (N is an integer greater than or equal to two) and a phase correction circuit. The N-phase RTWO includes a closed-loop transmission line formed as a Moebius strip. The closed-loop transmission l...  
WO/2010/030572A3
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupl...  
WO/2010/041606A1
Provided are a hysteresis comparator and a noise generator which can significantly reduce the circuit size. Provided is also a probability resonator using the hysteresis comparator and the noise generator. When the voltage (Vs) at the ...  
WO/2010/034326A1
An embodiment of a state machine (200) for generating a pseudo-random word stream, each word of the word stream comprising a plurality of subsequent bits of a pseudorandom bit sequence comprises a plurality of clock registers (210) and a...  
WO/2010/031630A1
An apparatus (1) for generating a random bit sequence (ZZ) comprises a ring oscillator which includes a plurality of inverting digital devices (2-11) and on which an oscillator signal (OS) can be tapped. An intermediate storage element (...  
WO/2010/033079A1
A relaxation oscillator and a method for offset cancellation in a relaxation oscillator. The relaxation oscillator comprises two comparator units, each comparator unit comprising a comparator element and a memory element; and a switch co...  
WO/2010/032659A1
A disturbance detection circuit is provided with a system in which a plurality of disturbance detection logic gates (G1 to Gn) each of which changes the logic value of the output in response to occurrence of a disturbance within the circ...  
WO/2010/029098A1
A level shifter (21) comprises a first stage (22) and a second stage (23). The first stage (22) comprises first and second inputs (34, 35) and is configured to generate a first signal (37) which indicates in a first state if either at le...  
WO/2010/030572A2
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupl...  
WO/2010/030577A1
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupl...  
WO/2010/026616A1
Timing setting data (T1-Tn) include an arbitrary combination of set timing signals (S), which are indicative of the timings of positive edges, and reset timing signals (R) which are indicative of the timings of negative edges. A sorting ...  
WO/2010/027915A2
A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled bet...  
WO/2010/023469A1
A method of measuring a very low frequencycomponent of a signal is described. The method comprises sampling the signal at random timesto generate a "decimated" signal, and then filtering the decimated signal using a low-passfilter. There...  
WO/2010/017772A1
The present invention provides apparatuses, methods, and computer readable media for supporting communications for a plurality of transmitter-receiver pairs on a common frequency spectrum. A transmitting device transmits a consecutively ...  
WO/2010/017643A1
There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input puls...  

Matches 701 - 750 out of 26,704