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WO/2015/073189A1 |
Technologies are generally described for quadrature -based injection- locking of ring oscillators. In some examples, an external signal may be injected into a ring oscillator. Phase signals may be measured from within the ring oscillator...
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WO/2015/069903A1 |
A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the ...
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WO/2015/066142A1 |
The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters (204, 205 and 206, 207) are configured back to back to latch a signal. Each inverter includes a capacitor (C1, C2) configured bet...
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WO/2015/065683A1 |
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...
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WO/2015/057923A1 |
A remote device in accordance with the present invention includes an adaptive power receiver that receives wireless power from the wireless power supply by induction. The adaptive power receiver may be switched among two or more modes of...
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WO/2015/050865A1 |
A ring oscillator comprising three or more delay cells, each of which comprises a plurality of differential input leads and a differential output lead, wherein each of the plurality of differential input leads comprises one or more inver...
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WO/2015/050621A1 |
One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second bi...
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WO/2015/042814A1 |
The present invention provides an injection locked frequency multiplier. The injection locked frequency multiplier comprises: an input stage, configured to receive an input signal having a first frequency, and generate a harmonic current...
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WO/2015/047280A1 |
Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupl...
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WO/2015/037086A1 |
This invention uses a vertical transistor, namely a surrounding gate transistor (SGT), to provide a semiconductor device that constitutes part of a latch circuit and has a small surface area. In said latch circuit, which comprises a plur...
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WO/2015/039049A1 |
Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled t...
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WO/2015/037252A1 |
The objective of the invention is to provide an oscillation circuit that ensures oscillation frequency precision against parameter variations, such as temperature variations, even for a relatively high frequency band. The oscillation cir...
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WO/2015/030150A1 |
The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in s...
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WO/2015/030937A1 |
An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operati...
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WO/2015/025682A1 |
A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5). The delay circ...
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WO/2015/023516A1 |
A functional timing sensor includes a setup time violation detecting circuit, a hold time violation detecting circuit, and an interface from the setup time violation detecting circuit and the hold time violation detecting circuit. The in...
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WO/2015/017307A1 |
An oscillating circuit with linear gain is presented. The oscillating circuit may include a relaxation oscillator and a current compensation block. The relaxation oscillator includes a capacitor, a pair of resistors operative to deliver ...
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WO/2015/017233A1 |
Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a f...
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WO/2015/014304A1 |
An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the fir...
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WO/2015/016734A1 |
A spread-spectrum clock generation circuit comprises at least one comparison element; at least one charge storage device arranged to couple an output of the at least one comparison element to an input of the at least one comparison el...
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WO/2015/009716A1 |
Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of t...
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WO/2015/005992A1 |
A flip-flop having a first storage circuit having a first input fed by the true logic signal and a second input fed by the complement of the logic signal. A second storage circuit has a pair of inputs coupled to the first storage circuit...
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WO/2015/001388A1 |
An oscillator circuit (201) of the type comprising a flip-flop (219) for generating a clock signal (222) and two comparators (213, 216) for comparing a reference voltage with the voltage across a first capacitor which is charged during a...
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WO/2015/001731A1 |
A semiconductor device is provided with: a first transistor and a second transistor that are connected in series via a first node; a third transistor and a fourth transistor that are connected in series via a second node; and a first fus...
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WO/2015/000640A1 |
The invention relates to a method for generating a number of random bits by means of an electronic oscillating circuit, wherein signals are simultaneously sensed or sampled at various points within a random number generator. An optionall...
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WO/2014/208470A1 |
Provided is a voltage regulator, wherein power consumption is small, and an NMOS transistor is used as an output transistor. This delay circuit is configured by providing, between a constant current circuit and a capacitor, a depression ...
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WO/2014/209716A1 |
In one example, a high-speed divider (38) includes two identical pseudo-CML latches (L1, L2) and four output inverters (70-73). Each latch includes a pair of cross-coupled signal holding transistors (MN1, MN2, MN7, MN8). A first P-channe...
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WO/2014/209715A1 |
A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b)...
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WO/2014/203466A1 |
This random number generating device comprises: an arithmetic random number generating unit (3) which generates an arithmetic random number series; an arithmetic random number conversion unit (5) which reads out one or more arithmetic ra...
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WO/2014/202074A1 |
The invention relates, inter alia, to an optoelectronic oscillator (10) for generating an optical and/or electric pulse comb, comprising a monolithically integrated passively mode-coupled semiconductor laser (20) and an optical feedback ...
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WO/2014/201031A1 |
An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a...
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WO/2014/197004A1 |
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a f...
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WO/2014/193254A1 |
This invention refers to modular generators to output bipolar or unipolar voltage pulses with corrected pulse voltage decay and respective process. The pulse correction and the respective process are integrated in p modules, of the n+p g...
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WO/2014/191201A1 |
The invention relates to a device and to a method for generating random bits by means of an electronic oscillating circuit having a plurality of representation apparatuses. Signal changes propagating in the oscillating circuit are stoppe...
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WO/2014/185923A1 |
Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit cou...
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WO/2014/184388A1 |
The system comprises: - a set of at least two electric current generators (101) - at least one capacitor (102) - activation/deactivation means (103) for activating/deactivating said electric current generators (101); the means for genera...
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WO/2014/179944A1 |
A flip-flop circuit may include a first latchand a second latch. The first latch, which may operate as a "master" latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an ...
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WO/2014/177300A1 |
The invention relates to a system (1) for generating random bits (ZB) comprising: a plurality of imaging devices (21 - 2m), wherein a respective imaging device (21 - 2m) is configured to image a predetermined number n of input signals (E...
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WO/2014/173553A1 |
The present invention relates to an apparatus and a method for generating high-voltage pulses, in particular by means of an inductive voltage adder IVA, wherein a coupling-in inductance (L) for each stage (13) is formed as a number of di...
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WO/2014/173576A1 |
The present invention relates to an apparatus and a method for generating high-voltage pulses, in particular by means of an inductive voltage adder (IVA), wherein an inner conductor (I) of a coaxial transmission line (21) is in the form ...
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WO/2014/170164A1 |
The present invention relates to an apparatus and a method for generating high-voltage pulses, particularly by means of an inductive voltage adder (IVA), wherein the first stage (17) contains an electromagnetically coupling funnel-shaped...
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WO/2014/167068A1 |
The invention concerns a device for controlling at least one diode 2, the control device comprising an electrical card 4 comprising a printed circuit 5 on which the following are mounted: a diode 2, a front component 7 and a storage capa...
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WO/2014/168838A2 |
A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. T...
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WO/2014/163881A1 |
A voltage controlled oscillator (VCO) which can be configured with a smaller tuning range than is ordinarily required is presented. Ordinarily, the tuning range is selected much broader than the application warrants so that sufficient ra...
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WO/2014/164311A1 |
A circuit to a extend signal comparison voltage range includes a latching circuit (402) and a comparator (404) responsive to common-mode input signals (Vin+, Vin-). The comparator (404) is coupled to the latching circuit (402) and to a d...
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WO/2014/158035A1 |
A diode (or a semiconductor circuit functionally equivalent to a diode) is formed in the upper surface of a silicon substrate. Resonating element mounting pads are formed on the same substrate surface and a resonating element is mounted ...
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WO/2014/157019A1 |
A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Dat...
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WO/2014/154414A1 |
The invention relates to an inductive tension addition unit (1), comprising a coaxial conductor structure comprising an internal conductor (2) and an outer conductor (3) that is divided into a plurality of outer conductor sections (4) co...
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WO/2014/150615A1 |
A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has ...
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WO/2014/153472A1 |
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire opendrain link by determining a transition in a signal received from the multi-wire...
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