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Matches 851 - 900 out of 26,916

Document Document Title
WO/2009/137240A2
The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions (730-739) between a first Josephson junction (710) and a second Josephson junction (720), the first J...  
WO/2009/136875A1
Presented is an improved design or redesign concept for synchronous sequential logic devices using an alternative type of registers. Further a suitable clock-tree concept for such registers is proposed. 2.2. The special registers typical...  
WO/2009/133300A1
The present invention relates to a high-voltage pulse generator comprising a “frozen-wave” generation system (1) for generating high-voltage pulses and a trigger system (2) for triggering said pulses, said generation system (1) compr...  
WO/2009/133658A1
Provided is a multiple signal switching circuit using four input signals (IN1 to IN4), wherein a 4-input latch circuit (3b) is disposed. The 4-input latch circuit (3b), when one of the four input signals (IN1 to IN4) is a logical “L”...  
WO/2009/133749A1
A digital logic circuit comprises a plurality of transistors of a same conduction type. A first transistor (40) has a source, gate and drain connected to a first circuit node (QB), a second circuit node (Y) and a first power supply line ...  
WO/2009/058995A3
The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse gene...  
WO/2009/128044A1
A method for alleviating burn-in effect and enabling performing a start-up process in respect of a device comprising a plurality of challengeable memory elements, wherein the memory elements are able to, upon start-up, generate a respons...  
WO/2009/128746A1
The invention describes self-timed implementations of single-stage and two-stage self-timed triggers with single-rail data input. Declared goal is succeeded due to that into circuit containing storage unit (2) with element indicating tra...  
WO/2009/127848A2
A clock distribution buffer, and a local oscillator circuit comprising a clock pulse generator and one or more such buffers, that provides efficient power consumption across a wide range of operational frequencies of a local oscillator. ...  
WO/2009/128921A2
The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5,...  
WO/2009/127757A1
The invention relates to a capacitance/frequency converter with a variable capacitance as an oscillator power supply source, including a variable capacitance device (300) which powers an oscillator (400) which supplies a pulse train (Vpu...  
WO/2009/124145A2
A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate ...  
WO/2009/122598A1
There is provided a logic circuit with a simple configuration and a good current efficiency. The logic circuit comprises a two-terminal bistable switching element (1) having a characteristic of maintaining a state, a first switching elem...  
WO/2009/115865A1
A latch module comprising a sense pair of transistor elements (T1 , T2) coupled together for sensing a differential input signal at input terminals (D, Dn), a level-shift module (T5, T6) for producing a differential output signal at outp...  
WO/2009/116176A1
According to a pseudo-pulse generator, integrator circuits are so configured that, among plural stages of the integrator circuits which output pseudo-pulses through integration over time, an amplifier constituting an integrator circuit i...  
WO/2009/113657A1
Provided is an oscillator using a high-frequency crystal oscillator element which satisfies the excitation level required for the crystal oscillator element and can widen the variable frequency range. A limiter circuit (LM1), which has i...  
WO/2009/027130A9
The invention relates to a device (1) for generating a random bit sequence with a digital ring oscillator circuit (2) comprising logic components, said circuit comprising an input node (3) and an output node (4), wherein the digital ring...  
WO/2009/110826A1
The invention relates to a capacitor arrangement (1) comprising at least one capacitor (2) having a first electrode (3) connected to a first conductive element (13) and a second electrode (4) connected to a second conductive element (14)...  
WO/2009/110086A1
In a latch circuit with scan (1), main latch circuits (Masters 1-4) corresponding to data inputs (D1-4) are connected in series, in the main latch circuits (Masters 4) of stages other than a last stage, the scan output of their own circu...  
WO/2009/104358A1
A plurality of multistage delay circuits (MD1 to MD5) each have n output terminals (n is a natural number). Each of the multistage delay circuits (MD1 to MD5) delays the input signal and outputs n delayed signals with different delay tim...  
WO/2009/104129A2
An electronic circuitry based on current-mode logic is provided which comprise a logic unit (LP) having a plurality of latch logic units (L1, L2, LN) each with a hold node (H1 - HN) and a sample node (S1 - SN) and a clock unit (CP) havin...  
WO/2009/101015A1
A digitally controlled oscillator comprising: an oscillator core configured to output an adjustable frequency output; and an oscillator tuner comprising at least one switchable impedance stage configured to control the oscillator core fr...  
WO/2009/062130A3
Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel tran...  
WO/2009/099499A2
A circuit (10) has first latch (30), a second latch (32), a coupling circuit (39), and a power down circuit (34). The first latch (30) has an input/output coupled to a data node (27). The second latch (32) has an input/output. The coupli...  
WO/2009/097315A1
In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The met...  
WO/2009/095717A1
An improved regenerative clocked sampling circuit is described which uses a single clocking signal to switch the circuit between a tracking phase in which the state tracks the input signal, and a bistable phase during which the state rap...  
WO/2009/091287A1
The invention relates to radio engineering and experimental medicine. The aim of the invention is to extend functionalities of an N-frequency harmonic and pulse signal generator by ensuring the operation thereof in a broad-band range wit...  
WO/2009/089403A1
A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of t...  
WO/2009/084524A1
Provided is a random number generation mechanism based on a normal distribution not causing a sequence correlation. The random number generation mechanism based on a normal distribution includes: a random recurrence plot generation mecha...  
WO/2009/078242A1
A non-volatile latch circuit comprises a latch circuit (11), first and second magnetoresistive elements (13-1, 13-2), and a current supply section (12). The latch circuit (11) temporarily holds data. The first and second magnetoresistive...  
WO/2009/078118A1
A magnetic path is formed by a magnetic detector (24) or (26) (more specifically, a magnetic wire (70)), the magnetic pole of a magnet (22), and a rotating shaft (20) as a motor rotates. Since the magnetic wire (70) consists of a magneti...  
WO/2009/073556A1
Devices and methods are provided for boosting a battery voltage and driving an actuator with programmable voltage shapes. In one embodiment, there is provided a device (e.g., an actuator driver) that includes: a boost circuit coupled to ...  
WO/2009/072511A1
A non-volatile latch circuit comprises first and second inverters connected in a cross-coupled configuration so as to hold one-bit data, first and second magnetoresistive elements each having first to third terminals, and a current suppl...  
WO/2009/072268A1
A delay circuit (100) includes a MOSFET (1) and bias voltage sources (12a, 12b). The bias voltage sources (12a, 12b) apply voltage across a drain and a source of the MOSFET (1). The bias voltage source (12a) supplies a source voltage Vss...  
WO/2008/153777A3
An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source cou...  
WO/2009/069597A1
Both high speed and high reliability in synchronization with a clock signal are balanced. A synchronization device for inputting an asynchronous signal and a clock signal and outputting a synchronous signal synchronized with the clock si...  
WO/2009/068164A1
The present invention relates to a circuit and a method for operating a consumer (10) comprising a power source (1) for providing a power supply to a consumer (10). A first switch (7) connected in parallel to a series circuit comprising ...  
WO/2007/033045A3
A stacked MOSFET includes a first transistor or MOSFET (202) connected to a bias voltage through bias resistor Rbias.The gate of transistor (202) is grounded through a capacitor (206) The output of the stacked MOSFET arrangement is taken...  
WO/2009/038846A3
A bipolar pulse forming transmission line module and system for linear induction accelerators having first, second, third, and fourth planar conductors which form a sequentially arranged interleaved stack having opposing first and second...  
WO/2009/066765A1
To generate a pulse signal having a desired pulse width. There are included a ring oscillator circuit including a plurality of series-connected delay circuits; rising and falling signal generating parts each of which is connected to a re...  
WO/2009/063948A1
An M-sequence generating circuit, which is applicable to a random error generating apparatus, has a plurality of registers that are cascade connected and a plurality of exclusive-OR gates that feed bit data stored in the respective regis...  
WO/2009/063542A1
A semiconductor device is characterized in that it includes latch circuits (103, 104) each having a plurality of data retention nodes, a first capacitive element (C) connected to the first data retention node (A) included in the pluralit...  
WO/2009/060625A1
A nonvolatile latch circuit comprises a latch circuit (6), output terminals (8, 9) of two inverters constituting the latch circuit, a first inverter (INV1) connected with one end of the operating current passage of one inverter, a second...  
WO/2009/062130A2
Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel tran...  
WO/2009/058995A2
The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse gene...  
WO/2009/027468A3
An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second su...  
WO/2009/054183A1
Intended is to prevent the overheat of a spin valve element. Provided is a driving method for feeding the spin valve element with a drive current thereby to acquire an oscillating signal. The driving method comprises the step of subjecti...  
WO/2009/024717A3
The invention relates to a test device (20) for an analog circuit (12) to be mounted on a mixed circuit (10) including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator (22) connected ...  
WO/2009/023719A3
A square-function circuit (10) includes an input field-effect transistor (FET) (12) having a gate that is driven by an input voltage (V1N, V1N2) and is configured to conduct an output current (IOUT)- The circuit also includes a feedback ...  
WO/2005/050392A3
A signal processing system distributes an input signal over a plurality of shaped signal distribution structures that are interconnected with a plurality of shaped signal pickup units. The signal distribution structures and/or the signal...  

Matches 851 - 900 out of 26,916