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Matches 51 - 100 out of 26,717

Document Document Title
WO/2019/140424A1
A fast startup power oscillator transmitter includes a transistor pair that drives a resonant circuit including a tunable capacitance. A capacitor array preferably forms the tunable capacitance. A voltage booster activates the capacitor ...  
WO/2019/136545A1
The method for generating a random bit sample involves a quantum tunneling barrier. The method generally has: generating a current of charges tunneling across said quantum tunneling barrier, the current of the tunneled charges having an ...  
WO/2019/139799A1
A capacitively-driven tunable coupler includes a coupling capacitor (110) connecting an open end of a quantum object (104) (i.e., an end of the object that cannot have a DC path to a low-voltage rail, such as a ground node, without break...  
WO/2019/133362A1
A surgical instrument is disclosed. The surgical instrument includes an electric motor and a control circuit. The control circuit includes a plurality of logic gates and a monostable multivibrator. The monostable multivibrator is connect...  
WO/2018/236883A8
A parallel Marx generator topology capable of producing high power, high current output pulses is provided. The parallel Marx generator topology can include a plurality of Marx generators that operate in parallel to one another to jointl...  
WO/2019/128235A1
A learning block (200) can be placed in parallel to an oscillator circuit (100) to control noise injection during the startup of a crystal oscillator. The learning block (200) can be configured to control the noise injection during the s...  
WO/2019/133001A1
A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual -input inverter, a single-input tri-state inverter, a dual -input tri-state inverter, and two single-event transient (SET) filters. The sing...  
WO/2019/125236A1
A clock signal polarity controlling circuit (100) comprises a first latch (110) comprising a clock input (clk), a data input (D) and an output (Q). The data input (D) is coupled to an output (121) of a clock signal generator (120), the c...  
WO/2019/120991A1
Method for activating a feature of a chip(10) having an interface (20) comprising at least two power pins (GND, VCC). The method comprises the following steps: -the chip measures a series of voltage values between said power pins, -the c...  
WO/2019/119228A1
Embodiments of the present invention provide a method and apparatus for updating time, and a movable platform. The method comprises: obtaining at least two change amounts of a counter within a first preset period; averaging the at least ...  
WO/2019/115316A1
An oscillator circuit arrangement comprises an inverter having input and output terminals (XIN, XOUT) that are to be connected to a crystal device. An automatic gain control device (AGC) controls a current source (MP2) that supplies curr...  
WO/2019/116764A1
The purpose of the present invention is to control, in an oscillator circuit using a comparator, the charging/discharging of a mirror capacitance between gate and drain of a MOSFET used as an amplifier in a gain section of the comparator...  
WO/2019/112849A1
A system and method for generating a radio frequency (RF) waveform are described. The method includes defining a train of on-off pulses separated by an off state having no on- off pulses. The method further includes applying a multi-leve...  
WO/2019/105590A1
A cascading microwave directional amplifier (cascade) (302) includes a set of Josephson devices (302(1)-302(n)), each Josephson device in the set having a corresponding operating bandwidth (BW(1)-BW(n)) of microwave frequencies (f1-fn), ...  
WO/2019/105242A1
Provided are a pulse voltage generation device, method, and controller, said device comprising: a transformer; a first AC/DC conversion circuit, the alternating-current side of which is connected to the high-voltage side of said transfor...  
WO/2019/105593A1
A cascading microwave isolator (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies. Different operating bandwidths have different correspondi...  
WO/2019/106225A1
A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal i...  
WO/2019/105931A1
A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (M1, M2, M3, M4) a...  
WO/2019/106226A1
Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well a...  
WO/2019/105594A1
A cascading selective microwave isolator includes a set of Josephson devices (110), each Josephson device (110) in the set having a corresponding operating bandwidth of microwave frequencies. Different operating bandwidths have different...  
WO/2019/097532A2  
WO/2019/094159A1
A reciprocal quantum logic (RQL) phase-mode flip-flop includes a storage loop and a comparator, each of which includes Josephson junctions (JJs). A data input, provided as a positive or negative single flux quantum (SFQ) pulse, is stored...  
WO/2019/094929A1
A plasma ion source includes a plasma chamber body having at least one inlet for introducing a feed gas to an interior of the plasma chamber body. The plasma chamber body is electrically isolated from a vacuum chamber attached to the pla...  
WO/2019/082190A1
A bandgap reference (BGREF) circuit includes at least one switch capacitor impedance element including a capacitor coupled with switches that receive a reference frequency. The at least one switch capacitor element is coupled with at lea...  
WO/2019/077890A1
The purpose of the present invention is to enable an oscillator circuit using a comparator to control charging/discharging of a mirror capacitance between the gate and the drain of a MOSFET serving as an internal amplifier of a gain unit...  
WO/2019/073788A1
The semiconductor circuit according to the present disclosure is provided with: a volatile first storage unit; a volatile second storage unit that stores, on the basis of a first control signal, data that has been stored in the first sto...  
WO/2019/074708A1
Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An inpu...  
WO/2019/068769A1
An arrangement (10) is disclosed, comprising at least one switching element (50) including a terminal (53), a switching element terminal sourcing and/or sinking circuit (95) connected to the at least one switching element and arranged fo...  
WO/2019/069056A1
The present techniques disclose a logic gate for an adaptive voltage scaling monitor, the logic gate comprising an inverting output and further comprising an imbalance between the drive strength of an NMOS component and a PMOS component ...  
WO/2019/067363A1
Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an outpu...  
WO/2019/063116A1
A signal generating system is provided. The signal generating system provides a microwave signal to a plurality of qubits. The signal generating system includes a generator, an oscillator, a mixer, and a splitter. The oscillator generate...  
WO/2018/203942A3
Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set...  
WO/2019/048919A1
The invention relates to a circuit comprising a DC-to-DC converter and an input circuit which is connected on the line side of the DC-to-DC converter and has a first terminal and a second terminal for connection to a power supply, and a ...  
WO/2019/040323A1
Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edg...  
WO/2019/040240A1
A flip-flop (100) is provided that includes a sense-amplifier-based master latch (105) clocked by a first edge of a delayed version of a clock signal (120out). A slave latch (110) includes a cross-coupled pair of logic gates for latching...  
WO/2019/040949A1
Some embodiments include a high voltage waveform generator comprising: a generator inductor; a high voltage nanosecond pulser having one or more solid state switches electrically and/or inductively coupled with the generator inductor, th...  
WO/2019/037430A1
A power supply circuit and a display device. The power supply circuit comprises: a power management integrated module (10) comprising a driving pin (11), the driving pin (11) being used for transmitting a driving signal; and a power tran...  
WO/2019/033306A1
Disclosed by the present invention are a method and apparatus for the dynamic adjustment of pulse width modulation signals: determining a target duty cycle and a number of bits of control precision; determining a number of bits for pulse...  
WO/2019/036154A1
A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circu...  
WO/2019/036179A1
A hybrid pulse-width control circuit is provided that includes a ramp voltage generator for generating a ramp voltage signal. A clock pulse generator asserts an output clock signal responsive to the ramp voltage signal equaling a referen...  
WO/2019/030667A1
Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS'), which have outputs (o-GPRS, o-GPRS') connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detecto...  
WO/2019/030669A1
Metastability based random number generator comprises an adjustable speed oscillatory response multivibrator (MOORS), having an output (Q) connected to an input (TQ) of a counter (LCZ). The output (T) of the counter (LCZ) is connected to...  
WO/2019/032085A1
Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise...  
WO/2019/030668A1
Metastability based random number generator comprises a block for metastability generation of time intervals (GMICRS') having at least two outputs (T1, T2, T3, T4, T5) and at least one speed control input (RS1, RS2, RS3, RS4, RS5), and i...  
WO/2019/032899A1
A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply "clocks") fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB...  
WO/2019/029929A1
The invention relates to a reliably operating triggerable spark gap TFS with small dimensions. The spark gap has a base BP and a cap KP. A cathode K, an anode A, and a trigger electrode TE in the form of conductive coatings are formed on...  
WO/2019/023000A1
A superconducting bidirectional current driver (10) is disclosed. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch...  
WO/2019/015724A1
The invention relates to a follow-hold circuit, for converting an analog input signal into a digital output signal, having a hold capacity unit, having a voltage amplifier unit containing an input, to which an analog input voltage signal...  
WO/2019/016530A1
A waveform generator (200) configured to generate two waveforms (211, 213) of opposite polarity so as to provide a voltage gain across a load (207). The waveform generator (200) has a primary side circuit comprising a first inductor (201...  
WO/2018/222344A3
Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch...  

Matches 51 - 100 out of 26,717