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WO/2023/022881A1 |
A system (305) includes a first park circuit (310) having a signal input (312), an output (314), and a control input (316). The system also includes a first signal path (320) having an input (322) and an output (324), wherein the input o...
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WO/2023/017530A1 |
The present invention relates to a method that improves the growth, yield, chlorophyll content and nutrition value of plants through enhanced mobility of nutrients in soil, by subjecting the plants and soil to high frequency impulse wave...
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WO/2023/018672A1 |
An ultra-wideband electromagnetic source includes a voltage source and a pulser assembly electrically coupled to the voltage source. The pulser assembly includes a bipolar vector inversion generator (VIG) assembly, a peaking gap assembly...
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WO/2023/017902A1 |
Disclosed are a high-speed semiconductor device driving circuit and system for power. The semiconductor device driving circuit comprises a transformation unit, a rectification unit, a pulse shaping unit, and a driving voltage application...
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WO/2023/016080A1 |
The present invention relates to a high-precision clock circuit structure, comprising a charge/discharge current generating circuit, a linear voltage regulator circuit, a ramp generating circuit, a comparator circuit, and a trigger circu...
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WO/2023/018476A1 |
A True Random Number Generator circuit compatible with all chip manufacturing technologies including CMOS, using the different types of multiple entropy sources to enhance the different parameters of a single circuit which generates the ...
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WO/2023/016520A1 |
A synergistic pulse generation circuit, generation apparatus, and generation method. The synergistic pulse generation circuit comprises a first power supply, a first pulse generation module electrically connected to the first power suppl...
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WO/2023/013101A1 |
The present invention addresses the problem of suppressing fluctuation of an output oscillation frequency in a PLL circuit. According to the present invention, an oscillator oscillates at a predetermined oscillation frequency. An oscil...
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WO/2023/014491A1 |
An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second g...
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WO/2023/285647A1 |
The present disclosure relates to a circuit comprising: - a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DE...
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WO/2023/287799A1 |
Apparatuses and methods for controlling the drilling direction of an electrocrushing drill bit. Electrode sets, which may comprise one or more electrodes, are energized by one or more transformers and capacitors in various configurations...
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WO/2023/285727A1 |
Disclosed is an apparatus (100) and a method for facilitating a first frequency filtering and a second frequency filtering together with non-reciprocal frequency conversion for electromagnetic isolation. The apparatus may be used for ele...
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WO/2023/280332A1 |
Circuit wiring arrangement of a monophasic stimulator for transcranial magnetic stimulation, which comprises a stimulation capacitor (C1l) connected via a switch (S) and a limiting means (Rp) to a source (U) of a stimulation energy, whil...
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WO/2023/274928A1 |
An asynchronous circuit portion (2) for sampling an input signal (14) is provided. The asynchronous circuit portion comprises a sampling circuit portion (4) arranged to receive the input signal and to generate first and second sample sig...
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WO/2023/275551A1 |
Described is circuitry (200) for driving a power switching device (226), the circuitry (200) comprising: a control circuit (211 ) in a first power domain configured to generate a first power domain PWM pulse signal (208a, 208b, 208c, 208...
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WO/2023/273377A1 |
Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adju...
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WO/2022/271144A1 |
The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, anot...
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WO/2022/263704A1 |
Example embodiments relate to generation of qubit clock signals. A superconductive phase detector may receive a reference frequency signal across a boundary of a cryogenic environment. A superconductive oscillator may be configured to ge...
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WO/2022/266009A1 |
An application specific integrated circuit (ASIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The ASIC can include a supply and reference voltage generation circuit, a digital core, a clock genera...
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WO/2022/258034A1 |
The present invention relates to the technical field of pulses. Disclosed are a pulse generation apparatus and a pulse control method, for use in solving the problems that a larger pulse width is difficult to realize and radio-frequency ...
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WO/2022/260756A1 |
A radio frequency (RF) generator includes a pulse generator circuit configured to receive input signals indicative of a pulse pattern defining an envelope of a pulse RF signal. The pulse generator circuit stores data values defining powe...
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WO/2022/255828A1 |
The present invention provides an active compensation device that actively compensates for noise generated in a common mode on each of at least two high current paths. The active compensation device comprises: a sensing unit that generat...
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WO/2022/254077A1 |
A microwave power source comprises a Josephson junction or junction array and a resonant tank circuit coupled thereto and configured to resonate at one or more frequencies of Josephson oscillation. An output coupler is coupled to said re...
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WO/2022/256633A1 |
A circuit (100) is provided. The circuit includes a first master stage (102), a second master stage (112), a first slave stage (106) and a second slave stage (116). The first master stage (102) includes a data input line (datain). The se...
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WO/2022/249584A1 |
A comparator circuit (30) according to the present embodiment comprises: a comparator element (31) that outputs an agreement signal indicating whether or not the value of a first input signal agrees with the value of a second input signa...
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WO/2022/249042A1 |
The present invention relates to a remotely triggered improved electrical stimulus circuit to be worn by cattle which is lightweight and can store voltage lower than what is to be supplied to an animal. Known cattle electrical stimulus c...
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WO/2022/249585A1 |
The present invention provides a low-power-consumption comparator circuit and a drive circuit. A comparator circuit (30) according to this embodiment comprises: a comparator element (31) that outputs a matching signal indicating whethe...
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WO/2022/240469A1 |
A circuit configured to transmit frequency multiplexed signals (208) from a superconducting domain (201) to a higher temperature domain (202). The circuit comprising a multiplexed signal output (208) and a plurality of superconducting os...
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WO/2022/237886A1 |
Disclosed in the present invention are a delay circuit, a pulse generation circuit, a chip and a server. The delay circuit comprises a control unit and at least two delay sub-circuits. Input ends of the delay sub-circuits are connected t...
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WO/2022/234169A1 |
A direct current to asymmetrical square wave alternating current converter, comprising: two direct current power sources A and B providing, respectively, output voltages VA and VB; and four switch devices (Q1, Q2, Q3 and Q4); where said ...
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WO/2022/233128A1 |
Provided are a capacitive touch detection circuit, a chip, and an electronic device. The capacitive touch detection circuit comprises an oscillation module (110), the oscillation module (110) comprising: a comparator (CMP), a charging an...
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WO/2022/232531A1 |
A controller and a method is provided for controlling a capacitance of an LC circuit having a circuit frequency including, a variable capacitor to couple with an external inductor as part of an LC circuit, a target value, a spread spectr...
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WO/2022/226462A2 |
This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimod...
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WO/2022/218213A1 |
The present application provides a pulse switching signal generating circuit and a pulse generating device. The pulse switching signal generating circuit (1) comprises a switching circuit (11), a driving circuit (12), and a pulse control...
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WO/2022/214881A1 |
A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able...
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WO/2022/209561A1 |
[Problem] To achieve frequency division with respect to an analog signal. [Solution] This frequency dividing circuit is provided with an inverter and an input circuit. The inverter includes a transistor. The input circuit converts a firs...
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WO/2022/211936A1 |
Topologies (110) for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network, RCN, that resonates in response to both a first clock signal (CLK+) havin...
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WO/2022/205547A1 |
The present invention relates to the technical field of integrated circuits, and in particular, to an ultra-low phase noise clock buffer. The ultra-low phase noise clock buffer of the present invention comprises a coupling capacitor, a f...
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WO/2022/212227A1 |
A real-time drug injection time duration measurement system includes a sound transducer, a waveform shaping circuit operably coupled therewith, a pulse clamping circuit operably coupled with the waveform shaping circuit, and a timer oper...
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WO/2022/204047A1 |
An apparatus comprises a plurality of power sources, one or more processors embedded with the plurality of power sources, and memory storing processor executable instructions that, when executed by the one or more processors, cause the a...
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WO/2022/202238A1 |
According to the present invention, a first switch (40) of this latch circuit (22) switches from off to on when a voltage between an emitter (input end) and a base (control end) in the first switch (40) rises to a voltage equal to or gre...
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WO/2022/204632A1 |
A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage ...
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WO/2022/198894A1 |
Embodiments of the present application provide a signal generation circuit and a memory. The signal generation circuit comprises: a clock delay module, configured to delay an initial pulse signal to output an intermediate signal, wherein...
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WO/2022/188353A1 |
The embodiments of the present application provide a pulse generation circuit and a staggered pulse generation circuit. The pulse generation circuit comprises: an oscillation module, which is used for receiving a control signal, and gene...
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WO/2022/191904A1 |
An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may f...
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WO/2022/187643A1 |
A ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last ...
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WO/2022/187498A1 |
A square wave oscillator includes a Schmitt Trigger (101) with a first output that outputs a first output current, a capacitor (103) connected to the first output of the Schmitt Trigger (101), and a resistor (105) that connects the capac...
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WO/2022/187226A1 |
A system and method for differentiating between different modes of pulsed electrical discharges via of an amplitude to time (ATC) conversion circuit is described. A bipolar ATC circuit is used to add together the positive and negative po...
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WO/2022/187529A1 |
A current-mode Schmitt Trigger (200) includes a plurality of current output stages (201A-C) connected to a common supply voltage that powers the current-mode Schmitt Trigger, a main input on one of the current output stages (201a) that r...
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WO/2022/179309A1 |
Disclosed in the present application are a clock management apparatus, a clock frequency division module and a system-on-a-chip. The clock management apparatus comprises a clock synchronization signal generator, a plurality of clock gate...
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