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Matches 151 - 200 out of 26,685

Document Document Title
WO/2018/052513A1
Systems and methods for process variation power control in three- dimensional integrated circuits, 3DICs, are disclosed. In an exemplary aspect, at least one process variation sensor (324, 326) is placed in each tier (302) of a 3DIC (300...  
WO/2018/048052A1
The present invention relates to an operational method for a random pulse generator which uses radioisotopes. The operational method for a random pulse generator which uses radioisotopes according to the present invention comprises the s...  
WO/2018/048912A1
Current generation circuitry for an Implantable Pulse Generator (IPG) is disclosed. The IPG comprises a plurality of PDACs and NDACs for souring currents to electrode nodes. The PDACs and NDACs can be configured as pairs to each provide ...  
WO/2018/048506A1
An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of...  
WO/2018/048572A1
Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal...  
WO/2018/010732A3
The invention relates to a device (200) for controllably delaying an electrical signal, the device comprising: - a first signal transfer path (207) between a signal input (201) and a signal output (204), the path having -- a first signal...  
WO/2018/044563A1
One example includes an isochronous receiver system. The system includes a single flux quantum (SFQ) receiver configured to receive a data signal from a transmission line and to convert the data signal to an SFQ signal. The system also i...  
WO/2018/044562A2
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/045223A1
In described examples, an apparatus (200) includes: a capacitor (230) having a first terminal coupled to receive a current and having a second terminal coupled to a ground; a first comparator (240) coupled to a voltage at the first termi...  
WO/2018/004765A3
A system (300) includes first and second sources (310, 311) configured to provide power to first and second medium-voltage direct current (MVDC) buses, respectively. The system also includes a rotating electrical machine (302) having fir...  
WO/2018/044383A1
A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered thr...  
WO/2018/044665A1
One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic oper...  
WO/2018/038854A1
An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coup...  
WO/2018/038398A1
A pulse power compensation device is disclosed. The present invention can supply a pulse power with a constant voltage without charge droop to a load by additionally installing a pulse power compensation device of a simple circuit struct...  
WO/2018/037192A1
The invention relates to a pulse generator (10) comprising an inductor (Lstock) that is intended to store energy that is delivered, during a charge phase, by a DC voltage source (30) to two power supply terminals of the generator (10), a...  
WO/2018/038817A1
An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionali...  
WO/2018/038833A1
An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.  
WO/2018/026084A1
Disclosed is a switching control circuit for controlling a switching unit included in a pulse power supply device. The present invention measures current supplied from a switching unit to a load to sense whether or not an arc occurs, and...  
WO/2018/022273A1
Methods and systems for independently tracking NMOS device process variation and PMOS device process variation are described herein. In one embodiment, a method for tracking process variation includes measuring a frequency (240) of an NM...  
WO/2018/017287A1
One embodiment describes a reciprocal quantum logic (RQL) receiver system. The RQL system is configured to convert a serial input data stream provided from a serial data transmitter into an RQL data stream. The RQL receiver system includ...  
WO/2018/015833A1
To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory circuit. The third terminal outputs "false" when "false" is input to the first ...  
WO/2018/014538A1
Disclosed are a relaxation oscillator and a single chip integrated chip. The oscillator comprises a relaxation oscillator circuit, wherein the relaxation oscillator circuit comprises a threshold voltage generation circuit (1), a capacita...  
WO/2018/014493A1
Provided are a comparator and a relaxation oscillator. The comparator comprises a comparator circuit. The comparator circuit comprises a current mode comparator circuit. The current mode comparison circuit comprises a first current mode ...  
WO/2018/013299A1
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first ...  
WO/2018/007545A1
The invention relates to an electric power supply system (1) for a Hall effect electric thruster, said Hall effect electric thruster comprising an anode (50), a cathode (51), a heating device (53) for the cathode and an igniter (52). The...  
WO/2018/008140A1
A pulse-width correction circuit (1) comprising: a fixing unit (10) that fixes an output signal S_OUT at a high level if, after a state in which the output signal S_OUT is low-level has continued for a first period of time, an input sign...  
WO/2018/009371A1
In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated ci...  
WO/2018/001701A1
A driving circuit (10)to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10).In a first operating state/pre-ch...  
WO/2018/005086A1
In one embodiment, a voltage level shifter (810) includes a first p-type metal-oxide-semiconductor transistor (835) having a gate configured to receive an input signal (D) in a first power domain, and a second PMOS transistor (840), wher...  
WO/2018/005085A1
A voltage level shifter includes a first NOR gate (250) having a first input (252) configured to receive a first input signal (D_N) in a first power domain, a second input (255) configured to receive an enable signal (ENB) in a second po...  
WO/2018/001146A1
A ring voltage-controlled oscillator, comprising: a conversion unit (100), a plurality of stages of cascaded delay units (200) and a plurality of stages of cascaded isolation buffering units (300). The conversion unit (100) receives a vo...  
WO/2017/222751A1
Various embodiments of methods and systems for closed loop multimode sleep clock frequency compensation in a portable computing device are disclosed. An exemplary embodiment leverages a modem to determine a frequency shift on a sleep clo...  
WO/2017/222620A1
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...  
WO/2017/223118A1
Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and...  
WO/2017/221544A1
The present invention performs input/output to/from a holding unit holding a result of analog-digital conversion by simple and easy control while preventing malfunction. An analog-digital conversion device is provided with a comparison u...  
WO/2017/213754A1
An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element for...  
WO/2017/209379A1
The present invention relates to a quantum random pulse generator having enhanced security by using a natural decay phenomenon of a radioactive isotope, the quantum random pulse generator comprising: a photo diode detecting unit having a...  
WO/2017/209844A1
A low clock power data-gated flip -flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR i...  
WO/2017/200718A1
An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a ...  
WO/2017/193594A1
A PWM circuit duty ratio adjustment method and system for a blood pressure measurement apparatus. The PWM circuit duty ratio adjustment method for a blood pressure measurement apparatus comprises the following steps: when a blood pressur...  
WO/2017/195614A1
The present invention relates to an oscillation circuit, an oscillation method, and a PLL circuit, whereby reduced power consumption and suppression of jitter (phase noise) degradation can be achieved at the same time. The oscillation ci...  
WO/2017/192059A1
A device for generating a high pulse voltage comprises a source of high constant voltage (1), an inductive load (2), two controllable switching devices (6) and (41), a controllable switch (25), and also, connected in series, a capacitor ...  
WO/2017/189806A1
A microelectromechanical resonant switch ("resoswitch") converts received radio frequency (RF) energy into a clock output. The resoswitch first accepts incoming amplitude- or frequency- shift keyed clock-modulated RF energy at a carrier ...  
WO/2017/185070A1
Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the rec...  
WO/2017/177243A1
The invention relates to a code generator, in which a plurality of flip-flops (R1, R2, R3) is interconnected to form a circuit. In addition, feedback is provided, wherein an output (Q) and an input (D) of the flip-flops (R1, R2) are recu...  
WO/2017/180447A1
A superconducting integrated circuit including a clock distribution network (600) for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network (600) may include a clock structure h...  
WO/2017/173526A1
A battery charging circuit can produce a pulsed charging current to charge a battery During charging, without disconnecting the pulsed charging current from the battery, EIS measurements can be made. In other words, the pulsed charging c...  
WO/2017/173295A1
In described examples, an integrated circuit IC (100A) provides an improved fail-safe signal (PKEEP2) to a module sharing a fail-safe pin at which a voltage can be greater than a voltage of an upper rail. The IC (100 A) includes: a first...  
WO/2017/172329A1
Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage (vdd1) of the first voltage domain and a second supply voltage (vdd2) of the second voltage domain are di...  
WO/2017/172116A1
An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits t...  

Matches 151 - 200 out of 26,685