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WO/2022/019968A1 |
Systems, methods, and devices for generation of narrow pulses in a flying high-voltage domain that are used as a timing control signal are presented. A main signal processing path that generates the timing control signal is replicated an...
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WO/2022/015549A1 |
Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only fre...
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WO/2022/015366A1 |
DC-DC power converter control comprises current starved delay lines for phase shifting control signals that set and reset a RS flip-flop to provide controllable PWM pulse widths from narrow to wide at a clock frequency. Precise pulse wid...
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WO/2022/010754A1 |
A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the...
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WO/2021/258824A1 |
An inverting output dynamic D flip-flop, comprising an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock si...
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WO/2021/260112A1 |
An oscillator circuit comprises a current controller (CC), a first capacitor (C1) and a second capacitor (C2). A current generator (CG) is coupled to the current controller (CC), the first and the second capacitor (C1, C2), and is operab...
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WO/2021/255343A1 |
A method for generating a voltage waveform (VS1(t), VF1(t)) comprises:- providing an optical signal (CLB1), which comprises one or more sequences of optical pulses (OPAT1,OPAT2), - distributing the optical pulses (OPAT1) via optical wave...
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WO/2021/255739A1 |
A high-resolution adaptive digital frequency synthesizer Integrated Circuit (IC) for wireless power systems, which comprises a digitally controlled tunable ring-oscillator, based on a chain of delay-line cells (DLs) being adapted to gene...
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WO/2021/255416A1 |
The present disclosure relates to driver circuitry for driving a capacitive transducer. The circuitry comprises: output stage circuitry (330) configured to receive an input signal and to drive the capacitive transducer (340) to produce t...
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WO/2021/254199A1 |
Provided in the present disclosure are a quick check circuit, a method and device therefor, solving the technical problem of poor user experience found in the prior art due to a low check speed and a long check time. The quick check circ...
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WO/2021/257724A1 |
A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters (72, 74) that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of th...
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WO/2021/252737A1 |
An output signal driver includes a positive output node, a negative output node, a power supply input node, a power supply common node, a charging capacitor, a discharging capacitor, a current source, a current sink, a first switch, a se...
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WO/2021/243451A1 |
Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurem...
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WO/2021/239031A1 |
A magnetoresistance relaxation oscillator type magnetometer (1), comprising: a capacitor (2), a charging resistor (3), a discharging resistor (4), a charging and discharging change-over switch (5), a high-voltage source terminal (6), a g...
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WO/2021/236402A1 |
Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, gen...
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WO/2021/232579A1 |
Disclosed is an N-type MOS high-side driver circuit that has a controllable slew rate, which belongs to the technical field of driver circuits and which uses a controllable current for the charging and discharging of the gate of a switch...
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WO/2021/229516A1 |
A modular apparatus (1) for generating high-intensity, pulsed electric fields for performing a treatment to inactivate pathogenic microorganisms present in a product or for extracting substances present in the product, comprises: a treat...
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WO/2021/228889A1 |
A time delay circuit comprising a plurality of differential delay cells 8 each having a respective time delay and being arranged in series. Each delay cell 8 comprises first and second inverter sub-cells 2a, 2b, each comprising a respect...
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WO/2021/216246A1 |
One example includes a superconducting latch system (50). The system includes a first input stage (52) configured to receive a first input pulse and a second input stage (54) configured to receive a second input pulse. The system also in...
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WO/2021/211112A1 |
According to examples, an apparatus may include an electrical connection for transmission of a reset signal from a controller to a peripheral device and a reset pull-down circuit coupled to the electrical connection. The reset pull-down ...
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WO/2021/207750A1 |
A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch...
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WO/2021/202451A1 |
Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector, PFD, (3110) which outputs differential error clocks based on comparison of differential reference clocks and differen...
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WO/2021/200361A1 |
This invention comprises a magnetic body that exhibits a large Barkhausen effect, a power generation coil disposed so as to be wrapped around the magnetic body, and a soft magnetic body that is formed on both ends of the magnetic body so...
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WO/2021/179836A1 |
An ultrahigh-precision digital pulse signal generation circuit and method. The circuit comprises: a pulse edge control circuit, configured to generate a specific amount of delay for a signal on an input pin Input and precisely control th...
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WO/2021/177517A1 |
Disclosed is a non-volatile flip-flop operation method in a data restoration mode. The present invention can maximize an offset removal effect by causing a first magnetic tunnel junction (MTJ) and a second MTJ to be disconnected from eac...
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WO/2021/178983A1 |
A device includes a temperature-variable voltage controller, in which the temperature-variable voltage controller comprises: a voltage regulator; a process monitor circuit coupled to the voltage regulator, in which the process monitor ci...
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WO/2021/165565A1 |
In a microelectronic circuit, a digital value (D) is temporarily stored in a register circuit (101). In relation to an allowable time limit defined by a triggering signal (CKP), there is stored a corresponding momentary value of said dig...
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WO/2021/161808A1 |
This bistable circuit comprises: a first inverter circuit and a second inverter circuit that each comprise a first FET in a channel, of a first conductivity type, of which the source is connected to a power line, the drain is connected t...
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WO/2021/155870A2 |
The present invention herein provides a voltage multiplier system for an electrical device. The system includes a multi-vibrator adapted to generate a clock signal, and a voltage-multiplier module. Further, the multi-vibrator includes a ...
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WO/2021/156658A1 |
Embodiments of apparatus and method for dynamic symbol pulse-shaping based on resource allocation are disclosed. In an example, a baseband chip includes a digital interface and a microcontroller operatively coupled to the digital interfa...
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WO/2021/153146A1 |
A fluctuation oscillator (1) is provided with: an adder (11) that has an input terminal (111) into which inputted is an input signal (S1) including a main signal and an uncorrelated signal which is uncorrelated to the main signal and has...
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WO/2021/152938A1 |
The present invention suppresses an unnecessary circuit operation caused by a toggle operation of a clock signal in a clock enabler circuit. A state holding unit performs a holding operation of a state of whether an output clock signal...
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WO/2021/144550A1 |
A power distribution circuit can include a comparator circuit that is formed of an inverter. The inverter can be configured with a trip voltage value (Vtrip) different than half a supply voltage value (VDD/2) for further energy efficienc...
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WO/2021/145987A1 |
Certain aspects of the present disclosure generally relate to a level- shifting circuit (100). The level-shifting circuit generally includes a first pull-up path (102, 170) having at least one first diode (170) and at least one first tra...
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WO/2021/145155A1 |
A fluctuating oscillator (1) is provided with a processor (10) formed from a digital circuit, and the processor comprises: a random variable generator (102) that generates a random variable; a lookup table (101) that stores in advance a ...
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WO/2021/142697A1 |
Provided are a clock signal generator, on-chip clock system, and chip; the clock signal generator (100) comprises: a first transistor (T1), a second transistor (T2), a flip-flop, and a power supply terminal; the first poles of the first ...
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WO/2021/141796A2 |
An electrical machine includes as part of its stator XRAM windings for multiplying current output of the machine. The XRAM windings are coupled to switching elements that are configured to produce current multiplication for output to an ...
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WO/2021/142411A1 |
An oscillator (31) for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal (such as for use in a transmitter for OOK pulse communication with pulse modulation). The oscillator (31) includes a...
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WO/2021/138730A1 |
A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillato...
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WO/2021/134651A1 |
Embodiments of the present application provide a device for calibrating the duty cycle of a clock. The device comprises a crystal oscillator, a buffer module, and a calibration module electrically connected in sequence. The buffer module...
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WO/2021/135102A1 |
Provided are a clock generation circuit and a latch using same, and a computing device. The cock generation circuit comprises an input end, used for inputting a pulse signal (CKI); a first output end, for outputting a first clock signal ...
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WO/2021/137693A1 |
The present invention discloses a resistor-capacitor oscillator, comprising a current bias circuit (12) with trimming resistors, a timing controller (13), a comparator (14), and a phase divider (16). The current bias circuit (12) has tri...
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WO/2021/133671A1 |
A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded...
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WO/2021/128924A1 |
Disclosed is a method for improving the current response speed of a pulse power supply. The method comprises: configuring an electrical energy storage and release module, a voltage sampling module, and a power component Q1 between a posi...
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WO/2021/133441A1 |
A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master- slave flip-flop utilizes novel layout optimization enabling ...
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WO/2021/128910A1 |
Provided in embodiments of the present application is a circuit and method for generating bimodal waveforms that comply with the IEC 61000-4-2 standard. The circuit comprises: a TLP generator circuit and a TLP external connection circuit...
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WO/2021/124322A1 |
Circuitry for reducing the energy losses of a snubber circuit used to protect current switching devices from overvoltage, comprising a switching cell consisting of a switch with alternating opposite conduction states, the switch being se...
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WO/2021/123903A1 |
A system comprising a quantum control data exchange circuit that enables a large, variable number of pulse generation circuits to exchange data within the coherence time of a plurality of quantum elements to enable feedback-based quantum...
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WO/2021/126405A1 |
An apparatus (20) and method for synchronizing a triggered system (System B) to a triggering system (System A) by tracking the timing of rising and falling edges of a clock signal (CLK_IN) at the triggered system and using the tracked ti...
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WO/2021/126373A1 |
A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of a...
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