| Document |
Document Title |
|
WO/2020/113537A1 |
A D flip-flop capable of preventing metastability comprises a potential control circuit (100) and, a first phase inverter (10), a first latch unit (20), a second phase inverter (30), and a second latch unit (40) that are sequentially cou...
|
|
WO/2020/117576A1 |
Superconducting circuits and methods for latching data are described. An example superconducting circuit includes an edge detect circuit (110) configured to receive a logical clock signal (LCLKIN) and generate a return-to-zero clock sign...
|
|
WO/2020/117577A1 |
Superconducting circuits and methods for detecting a rising edge of an input signal are described. An example superconducting circuit includes an input terminal for receiving an input signal comprising both positive pulses and negative p...
|
|
WO/2020/114081A1 |
Disclosed is a gas-tight environment-based high pulse current generation device having a nanosecond-scale rise time, the device comprising a gas-tight cavity having a pressure greater than or equal to the normal atmospheric pressure. An ...
|
|
WO/2020/109647A1 |
Microelectronic circuit com- prisesaplurality of logic units and register circuits, arranged into a plu- rality of processing paths, and a plu- rality of monitoring units associated with respective ones of said processing paths. Each of ...
|
|
WO/2020/112294A1 |
An inverting reciprocal quantum logic (RQL) phase-mode D flip-flop (300) accepts a data input (Dl) and a logical clock input (LCLKI). The flip-flop includes a stacked Josephson junction (J3) and a comparator (J5, J4). The triggering or u...
|
|
WO/2020/102896A1 |
Embodiments of the present disclosure disclose a method for improving a performance of a pulsed-ultraviolet (PUV) device. The method includes monitoring an input current across a circuit breaker in communication with a UV lamp, where the...
|
|
WO/2020/105182A1 |
This voltage-controlled oscillator (5) is provided with: a first transistor (M1) in which a gate is connected to an input terminal (PIN), a source is connected to a ground VSS, and a drain is connected to a first node (N1); a second tran...
|
|
WO/2020/101820A1 |
One example includes a superconducting transmission line driver system. The system includes an input stage configured to receive an input pulse and an AC bias current source configured to provide an AC bias current. The system also inclu...
|
|
WO/2020/098349A1 |
A clock cycle-based pulse width modulation signal duty cycle multiplication circuit, comprising: a duty cycle multiplication enabling pulse generating circuit (101), an input end thereof inputting a clock signal (CLK) and an original pul...
|
|
WO/2020/018716A9 |
A communicate device includes transmitters and a receiver. The first transmitter is coupled to a first 90º phase shifter that is also coupled to a first antenna, and to a second 90º phase shifter that is also coupled to a first node. T...
|
|
WO/2020/095041A2 |
Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are i...
|
|
WO/2020/096705A1 |
A tag includes: a housing configured for coupling the tag to a physical object to organize activities regarding the physical object; and coupled to the housing: a wireless communication component; circuitry electrically coupled to the wi...
|
|
WO/2020/090782A1 |
The present invention provides an electromagnetic-wave producing device that includes a plurality of electromagnetic-wave producing elements, wherein the instantaneous maximum power consumption at the time of an electromagnetic-wave prod...
|
|
WO/2020/077557A1 |
Provided in the present application are a duty cycle calibration circuit, an electronic device and a method, used to implement real time, bi-directional and highly accurate calibration of a duty cycle. The circuit comprises: a pre-proces...
|
|
WO/2020/079951A1 |
The purpose of the present invention is to minimize the sizes of data-holding circuits. First and second MOS transistors transmit a data signal and a reversed data signal, respectively, to input of first and second reversed gates constit...
|
|
WO/2020/072180A1 |
A wide supply range digital level shifter circuit (100) shifts between a variable desired output voltage (160) ranging from a first voltage level (digital high) and a second voltage level (digital low). The wide supply range digital leve...
|
|
WO/2020/068533A1 |
Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to mea...
|
|
WO/2020/068201A1 |
The various embodiments described herein include methods, devices, and systems for fabricating and operating superconducting circuitry. In one aspect, an amplification circuit includes: (1) a superconducting component; (2) an amplifier c...
|
|
WO/2020/068837A1 |
A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a c...
|
|
WO/2020/068236A1 |
Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory...
|
|
WO/2020/055746A1 |
An apparatus includes a clockless decision feedback equalization (DFE) loop (114A). The clockless DFE loop (114A) includes a summation circuit (116A) configured to combine a multi-level input signal (V_IN) and a multi-level feedback sign...
|
|
WO/2020/053570A1 |
Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or ...
|
|
WO/2020/050897A1 |
Examples described in this disclosure relate to a memory cell with Josephson phase-based torque. In one example, a memory cell including a first inductor and a magnetic Josephson junction (MJJ) coupled to the first inductor to form a loo...
|
|
WO/2020/050647A1 |
The present invention provides a method for driving an electronic device so that the electronic device can have a higher stability and a longer lifetime. More particularly, proposed is a method for driving an electronic device so that po...
|
|
WO/2020/044664A1 |
The purpose of the present invention is to stably adjust a duty cycle of a clock signal in the event of a drop in source voltage. The duty cycle correction circuit is equipped with an inverting buffer, a capacitor, a low-pass filter, an ...
|
|
WO/2020/045034A1 |
A semiconductor circuit of the present disclosure is provided with: a first circuit which generates an inverted voltage of a voltage at a first node and applies the inverted voltage to a second node; a second circuit which generates an i...
|
|
WO/2020/041362A1 |
Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include ...
|
|
WO/2020/039977A1 |
A semiconductor circuit device according to the present disclosure comprises: a control circuit that controls a clock signal input from the outside; a drive circuit that performs a switching operation according to a pulse signal provided...
|
|
WO/2020/041113A1 |
Aspects of the description provide a method (200). In some examples, the method includes detecting a transition in an input signal (IN) (205), generating a bias current based on the detected transition in IN (210), and modifying a charge...
|
|
WO/2020/031016A1 |
The present invention raises the output gain of a latch circuit. Provided are a first circuit, a second circuit, and a latch circuit having first to fourth transistors. The latch circuit has a first input/output terminal and a second inp...
|
|
WO/2020/033002A1 |
Disclosed herein is a true random number generator (TRNG). The TRNG includes a cavity filled with tritium and an electronic sensor constructed to detect energy from the decay of the tritium. The sensor produces a signal for the detected ...
|
|
WO/2020/033931A1 |
Some embodiments include a plasma sheath control system that includes an RF power supply producing an A sinusoidal waveform with a frequency greater than 20 kHz and a peak voltage greater than 1 kV and a plasma chamber electrically coupl...
|
|
WO/2020/032890A2 |
The present invention relates to a neuron circuit (1), which electronically applies the working principle of the neurons in human brain, controls an input signal according to a set threshold value, and enables to provide an output signal...
|
|
WO/2020/024889A1 |
The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2^n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2^n stages with...
|
|
WO/2020/027969A1 |
A reciprocal quantum logic (RQL) phase-mode D flip-flop accepts a data input and a logical clock input. A D flip-flop with an enable input further accepts enable input and further requires that the enable be asserted high to allow the da...
|
|
WO/2020/027972A1 |
Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a "body" circuit that provides a single or multi-state sub-critical bias current to one o...
|
|
WO/2020/023974A1 |
Some embodiments include a high voltage pulsing power supply. A high voltage pulsing power supply may include: a high voltage pulser having an output that provides pulses with an amplitude greater than about 1 kV, a pulse width greater t...
|
|
WO/2020/023965A1 |
A high voltage power system is disclosed. In some embodiments, the high voltage power system includes a high voltage pulsing power supply; a transformer electrically coupled with the high voltage pulsing power supply; an output electrica...
|
|
WO/2020/020760A1 |
The present invention relates to a device (1A, 1B) for pulsed electric discharge in a liquid, said device (1A, 1B) comprising at least one pair of electrodes (10) which are configured to be immersed in said liquid and to generate an elec...
|
|
WO/2020/023964A1 |
A plasma deposition system comprising a wafer platform, a second electrode, a first electrode, a first high voltage pulser, and a second high voltage pulser. In some embodiments, the second electrode may be disposed proximate with the wa...
|
|
WO/2020/011801A1 |
The invention relates to a digital isolator comprising a logic module (20) for receiving an input signal D, and providing command signals (41, 42) to sawtooth modulators. A first sawtooth modulator STM1 provides a first sawtooth signal a...
|
|
WO/2020/006649A1 |
A multi-bit flip flop (1). The multi-bit flip flop (1) comprises a clock input pin (PIN1), a clock buffer circuit (110), and multiple flip flops (121-128). The clock buffer circuit (110) is used for receiving a first clock signal (CP) fr...
|
|
WO/2020/007979A1 |
The present application provides a level shifter in integrated circuit with a reduced N-well spacing requirement.
|
|
WO/2020/006213A1 |
Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information dur...
|
|
WO/2020/005438A1 |
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communi...
|
|
WO/2020/001167A1 |
A dynamic D flip-flop (400, 500, 600) and a data operation unit (700) using same, a chip (800), a hash board (900) and a computing device (1000). The dynamic D flip-flop (400, 500, 600) comprises an input end (404), an output end (405) a...
|
|
WO/2019/245901A1 |
Improvements in a battery optimization and restoration device that uses a means of varying the regulator voltage as a function of time and discharge event timing and depth in order to establish a consistent power level for the charging o...
|
|
WO/2019/245902A1 |
Improvements in a battery optimization and restoration device that uses a means of varying the regulator voltage as a function of time and discharge event timing and depth in order to establish a consistent power level for the charging o...
|
|
WO/2019/237733A1 |
A narrow pulse generation circuit used in a sequential equivalent sampling system. The circuit comprises a crystal oscillator, an edge sharpening circuit, an avalanche transistor single-tube amplifying circuit and a shaping network conne...
|
