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Patent Searching and Data


Matches 401 - 450 out of 26,685

Document Document Title
WO/2014/201031A1
An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a...  
WO/2014/168838A3
A circuit (100) including a logic gate (133) responsive to a clock signal (103) and to a control signal (104). The circuit also includes a master stage (101) of a flip-flop. The circuit further includes a slave stage (102) of the flip-fl...  
WO/2014/197004A1
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a f...  
WO/2014/193254A1
This invention refers to modular generators to output bipolar or unipolar voltage pulses with corrected pulse voltage decay and respective process. The pulse correction and the respective process are integrated in p modules, of the n+p g...  
WO/2014/191201A1
The invention relates to a device and to a method for generating random bits by means of an electronic oscillating circuit having a plurality of representation apparatuses. Signal changes propagating in the oscillating circuit are stoppe...  
WO/2014/144582A3
An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one ...  
WO/2014/185923A1
Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit cou...  
WO/2014/184388A1
The system comprises: - a set of at least two electric current generators (101) - at least one capacitor (102) - activation/deactivation means (103) for activating/deactivating said electric current generators (101); the means for genera...  
WO/2014/179944A1
A flip-flop circuit may include a first latchand a second latch. The first latch, which may operate as a "master" latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an ...  
WO/2014/177300A1
The invention relates to a system (1) for generating random bits (ZB) comprising: a plurality of imaging devices (21 - 2m), wherein a respective imaging device (21 - 2m) is configured to image a predetermined number n of input signals (E...  
WO/2014/145066A3
Systems and methods for operating transistors near or in the subĀ¬ threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal (Ck) to a flop (15...  
WO/2014/173553A1
The present invention relates to an apparatus and a method for generating high-voltage pulses, in particular by means of an inductive voltage adder IVA, wherein a coupling-in inductance (L) for each stage (13) is formed as a number of di...  
WO/2014/173576A1
The present invention relates to an apparatus and a method for generating high-voltage pulses, in particular by means of an inductive voltage adder (IVA), wherein an inner conductor (I) of a coaxial transmission line (21) is in the form ...  
WO/2014/120416A3
A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latc...  
WO/2014/170164A1
The present invention relates to an apparatus and a method for generating high-voltage pulses, particularly by means of an inductive voltage adder (IVA), wherein the first stage (17) contains an electromagnetically coupling funnel-shaped...  
WO/2014/167068A1
The invention concerns a device for controlling at least one diode 2, the control device comprising an electrical card 4 comprising a printed circuit 5 on which the following are mounted: a diode 2, a front component 7 and a storage capa...  
WO/2014/168838A2
A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. T...  
WO/2014/163881A1
A voltage controlled oscillator (VCO) which can be configured with a smaller tuning range than is ordinarily required is presented. Ordinarily, the tuning range is selected much broader than the application warrants so that sufficient ra...  
WO/2014/164311A1
A circuit to a extend signal comparison voltage range includes a latching circuit (402) and a comparator (404) responsive to common-mode input signals (Vin+, Vin-). The comparator (404) is coupled to the latching circuit (402) and to a d...  
WO/2014/158035A1
A diode (or a semiconductor circuit functionally equivalent to a diode) is formed in the upper surface of a silicon substrate. Resonating element mounting pads are formed on the same substrate surface and a resonating element is mounted ...  
WO/2014/157019A1
A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Dat...  
WO/2014/154414A1
The invention relates to an inductive tension addition unit (1), comprising a coaxial conductor structure comprising an internal conductor (2) and an outer conductor (3) that is divided into a plurality of outer conductor sections (4) co...  
WO/2014/150615A1
A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has ...  
WO/2014/153472A1
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire opendrain link by determining a transition in a signal received from the multi-wire...  
WO/2014/139151A1
Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first...  
WO/2014/145066A2
Systems and methods for operating transistors near or in the sub-threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal to a flop via a cloc...  
WO/2014/146016A2
A multiple output current stimulator circuit with fast turn on time is described. At least one pair of input side and output side transistors is arranged in a current mirror connected to a supply transistor by cascode coupling. The outpu...  
WO/2014/143206A1
Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typicall...  
WO/2014/143046A1
Systems and methods for transpositional modulation and demodulation are provided. One such method for generating a signal includes the steps of providing a look-up table having a plurality of quarter-cycle waveforms, each of said quarter...  
WO/2014/140565A1
An assembly (100, 220, 300) that includes a laser diode (110, 310) and a driver circuit (120) that operates to give the assembly an (100, 220, 300) adjustable impedance. The driver circuit (120) adjusts impedance by repeatedly alternatin...  
WO/2014/138033A1
Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level...  
WO/2014/137736A1
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is pr...  
WO/2014/136399A1
An injection-locked oscillator (100) is provided with: a ring oscillator in which a first amplification circuit (141) that comprises an N-channel MOS transistor (111) and P-channel MOS transistors (112, 113) and a second amplification ci...  
WO/2014/137714A1
A particular method includes receiving a retention signal (nret). In response to receiving the retention signal, the method includes retaining state information (q internal, 310) in a non-volatile stage (302) of a retention register (300...  
WO/2014/137666A1
A system includes first circuitry including first elements for operating in a low power mode; second circuitry including second elements for operating in a high-temperature mode; and one or more switching elements for selecting between t...  
WO/2014/130174A1
A clock multiplier circuit (200) includes a clock generator (210), a delay element (220), a logic gate (230), and a duty cycle correction circuit (240). The clock generator (210) generates a clock signal (X). The delay element (240) gene...  
WO/2014/130754A1
A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency is disclosed. The numerical oscillator is controlled by a programmable numerical value being subject to a transfer func...  
WO/2014/130561A1
In an embodiment, a flip-flop circuit contains a 2-input multiplexer (102), a master latch 9104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determine whether data or scan...  
WO/2014/130560A2
A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprise...  
WO/2014/124037A1
In an embodiment of the invention, a flip-flop circuit (100) contains a 2-input multiplexer (102), a master latch (104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determi...  
WO/2014/124023A1
One feature pertains to an integrated circuit "IC" that includes a first plurality of ring oscillators (318) configured to implement, in part, a physically unclonable function "PUF". The IC further includes a second plurality of ring osc...  
WO/2014/120416A2
A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latc...  
WO/2014/116100A1
An on-chip controller for SSL driver (101) that includes control circuitry comprising Bipolar, CMOS and DMOS power devices on a single monolithic substrate is provided. The SSL driver control circuitry (101) includes a sensing stage and ...  
WO/2014/111328A1
The invention relates to a high-voltage pulse generator, in which the high-voltage pulses provided are transformed to a higher voltage level by means of a transformation network (3-i) before being coupled into a coaxial conductor arrange...  
WO/2014/111274A1
The invention relates to a pulse generator, preferably an inductive voltage adder, in which the energy is coupled purely inductively into the cavity (3) between the outer conductor (1) and the inner conductor (2). The inductive coupling ...  
WO/2014/111229A1
The invention relates to a device and a method for generating high-voltage pulses by means of high-voltage pulse generator stages (6R-i) which are inductively decoupled from one another and each of which inductively couples high-voltage ...  
WO/2014/110371A1
A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in...  
WO/2014/110566A1
A magnetic tunneling junction non-volatile register with feedback for robust read and write operations. In an embodiment, two MTJ devices (124; 126) are configured to store a logical 0 or a logical 1, and are coupled to drive an output n...  
WO/2014/094506A1
Disclosed is a small-sized rapidly-flip-flop Schmitt flip-flop circuit used for a silicon-on-insulator process, which changes the threshold voltage of a MOS transistor by adopting a PMOS/NMOS control circuit, so as to enable the input tr...  
WO/2014/094515A1
A discharge system for liquid phase pulses output in a time-delay manner based on multiple switches, comprising: a master circuit unit composed of n stages of discharge circuits and a drive unit. The drive unit is used for successively o...  

Matches 401 - 450 out of 26,685