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Matches 1 - 50 out of 26,239

Document Document Title
WO/2018/013299A1
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first ...  
WO/2018/007545A1
The invention relates to an electric power supply system (1) for a Hall effect electric thruster, said Hall effect electric thruster comprising an anode (50), a cathode (51), a heating device (53) for the cathode and an igniter (52). The...  
WO/2018/008140A1
A pulse-width correction circuit (1) comprising: a fixing unit (10) that fixes an output signal S_OUT at a high level if, after a state in which the output signal S_OUT is low-level has continued for a first period of time, an input sign...  
WO/2018/009371A1
In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated ci...  
WO/2018/001701A1
A driving circuit (10)to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10).In a first operating state/pre-ch...  
WO/2018/005086A1
In one embodiment, a voltage level shifter (810) includes a first p-type metal-oxide-semiconductor transistor (835) having a gate configured to receive an input signal (D) in a first power domain, and a second PMOS transistor (840), wher...  
WO/2018/005085A1
A voltage level shifter includes a first NOR gate (250) having a first input (252) configured to receive a first input signal (D_N) in a first power domain, a second input (255) configured to receive an enable signal (ENB) in a second po...  
WO/2018/001146A1
A ring voltage-controlled oscillator, comprising: a conversion unit (100), a plurality of stages of cascaded delay units (200) and a plurality of stages of cascaded isolation buffering units (300). The conversion unit (100) receives a vo...  
WO/2017/222751A1
Various embodiments of methods and systems for closed loop multimode sleep clock frequency compensation in a portable computing device are disclosed. An exemplary embodiment leverages a modem to determine a frequency shift on a sleep clo...  
WO/2017/222620A1
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...  
WO/2017/223118A1
Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and...  
WO/2017/221544A1
The present invention performs input/output to/from a holding unit holding a result of analog-digital conversion by simple and easy control while preventing malfunction. An analog-digital conversion device is provided with a comparison u...  
WO/2017/213754A1
An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element for...  
WO/2017/209379A1
The present invention relates to a quantum random pulse generator having enhanced security by using a natural decay phenomenon of a radioactive isotope, the quantum random pulse generator comprising: a photo diode detecting unit having a...  
WO/2017/209844A1
A low clock power data-gated flip -flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR i...  
WO/2017/200718A1
An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a ...  
WO/2017/193594A1
A PWM circuit duty ratio adjustment method and system for a blood pressure measurement apparatus. The PWM circuit duty ratio adjustment method for a blood pressure measurement apparatus comprises the following steps: when a blood pressur...  
WO/2017/195614A1
The present invention relates to an oscillation circuit, an oscillation method, and a PLL circuit, whereby reduced power consumption and suppression of jitter (phase noise) degradation can be achieved at the same time. The oscillation ci...  
WO/2017/192059A1
A device for generating a high pulse voltage comprises a source of high constant voltage (1), an inductive load (2), two controllable switching devices (6) and (41), a controllable switch (25), and also, connected in series, a capacitor ...  
WO/2017/189806A1
A microelectromechanical resonant switch ("resoswitch") converts received radio frequency (RF) energy into a clock output. The resoswitch first accepts incoming amplitude- or frequency- shift keyed clock-modulated RF energy at a carrier ...  
WO/2017/185070A1
Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the rec...  
WO/2017/177243A1
The invention relates to a code generator, in which a plurality of flip-flops (R1, R2, R3) is interconnected to form a circuit. In addition, feedback is provided, wherein an output (Q) and an input (D) of the flip-flops (R1, R2) are recu...  
WO/2017/180447A1
A superconducting integrated circuit including a clock distribution network (600) for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network (600) may include a clock structure h...  
WO/2017/173526A1
A battery charging circuit can produce a pulsed charging current to charge a battery During charging, without disconnecting the pulsed charging current from the battery, EIS measurements can be made. In other words, the pulsed charging c...  
WO/2017/173295A1
In described examples, an integrated circuit IC (100A) provides an improved fail-safe signal (PKEEP2) to a module sharing a fail-safe pin at which a voltage can be greater than a voltage of an upper rail. The IC (100 A) includes: a first...  
WO/2017/172329A1
Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage (vdd1) of the first voltage domain and a second supply voltage (vdd2) of the second voltage domain are di...  
WO/2017/172116A1
An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits t...  
WO/2017/157625A1
The invention relates to a device (I) and a method for generating a combustible gas from a mass (M), in particular a biomass, using a non-thermal plasma produced in a reactor (3), wherein an electric power supply system (7) that is contr...  
WO/2017/157026A1
Provided is a clock duty-cycle calibration and frequency-doubling circuit, used in the design of a square-wave frequency multiplier and relating to the technical field of integrated circuits, comprising: a gating module (301), which perf...  
WO/2017/160380A1
The present application discloses new approaches to providing passive-off protection for a B-TRAN-like device. Even if the control circuitry is inactive, AC coupling uses transient voltage on the external terminals to prevent forward bia...  
WO/2017/151275A1
A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circu...  
WO/2017/151260A1
A pulse generator discharge circuit is disclosed. The circuit includes one or more discharge stages, each discharge stage including a plurality of control input terminals. The circuit also includes first and second discharge terminals, a...  
WO/2017/151295A1
An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having...  
WO/2017/147895A1
In one example, an apparatus may be a flip-flop that includes a slave latch and a master latch. The master latch includes a first logic element in the master latch. The first logic element includes a first transistor. The first transisto...  
WO/2017/151301A1
A method of generating a bandgap voltage in an electronic circuit includes generating a bandgap current. The method further includes operating the electronic circuit using the bandgap voltage and the bandgap current. The operating can be...  
WO/2017/149978A1
[Problem] To provide a ring oscillator capable of controlling frequency according to the delay amount of a delay element, with a structure for which fine-level frequency setting is possible. [Solution] A reference signal generation devic...  
WO/2017/151261A1
A sub-microsecond pulsed electric field generator is disclosed. The field generator includes a controller, which generates a power supply control signal and generates a pulse generator control signal, and a power supply, which receives t...  
WO/2017/151293A1
In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first ...  
WO/2017/146650A1
Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third...  
WO/2017/143573A1
A pulse generating device, belonging to the field of distance measurement, comprising: a level generating module (01), a level conversion module (02), and a pulse generating module (03); the level generating module (01) generating, accor...  
WO/2017/144855A1
According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron switch, hereinafter termed CES, element. The latching circuitry furth...  
WO/2017/142664A1
Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multip...  
WO/2017/142696A1
The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The firs...  
WO/2017/133466A1
A high-speed low-power-consumption trigger, comprising a control signal generating circuit, an enabling unit and a latch structure, wherein the latch structure includes two input terminals, two output terminals, two enabling terminals, a...  
WO/2017/128647A1
A trigger and an oscillation system. The trigger comprises: a first voltage input end (1); a bias voltage input end (2); a first offset pipe (M5), which is configured with a scaling ratio relative to a first component of an external appa...  
WO/2017/129947A1
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage (212), a resistor (Rl), a capacitor (CI), and active switches (Ml, M2) arranged to provide a clock sign...  
WO/2017/124094A1
An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs...  
WO/2017/120002A1
A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal (320) in a first power domain (302) and initiate a second clock signal (3...  
WO/2017/118873A3
Layouts of transmission gates and related techniques and systems are described. An integrated circuit may include first and second transmission gates (150, 160) disposed in a column, and metal wires (174a, 174b, 188a). The first transmis...  
WO/2017/118873A2
Layouts of transmission gates and related techniques and systems are described. An integrated circuit may include first and second transmission gates disposed in a column, and metal wires. The first transmission gate includes first and s...  

Matches 1 - 50 out of 26,239