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Matches 1 - 50 out of 26,520

Document Document Title
WO/2019/094159A1
A reciprocal quantum logic (RQL) phase-mode flip-flop includes a storage loop and a comparator, each of which includes Josephson junctions (JJs). A data input, provided as a positive or negative single flux quantum (SFQ) pulse, is stored...  
WO/2019/094929A1
A plasma ion source includes a plasma chamber body having at least one inlet for introducing a feed gas to an interior of the plasma chamber body. The plasma chamber body is electrically isolated from a vacuum chamber attached to the pla...  
WO/2019/082190A1
A bandgap reference (BGREF) circuit includes at least one switch capacitor impedance element including a capacitor coupled with switches that receive a reference frequency. The at least one switch capacitor element is coupled with at lea...  
WO/2019/077890A1
The purpose of the present invention is to enable an oscillator circuit using a comparator to control charging/discharging of a mirror capacitance between the gate and the drain of a MOSFET serving as an internal amplifier of a gain unit...  
WO/2019/073788A1
The semiconductor circuit according to the present disclosure is provided with: a volatile first storage unit; a volatile second storage unit that stores, on the basis of a first control signal, data that has been stored in the first sto...  
WO/2019/074708A1
Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An inpu...  
WO/2019/068769A1
An arrangement (10) is disclosed, comprising at least one switching element (50) including a terminal (53), a switching element terminal sourcing and/or sinking circuit (95) connected to the at least one switching element and arranged fo...  
WO/2019/069056A1
The present techniques disclose a logic gate for an adaptive voltage scaling monitor, the logic gate comprising an inverting output and further comprising an imbalance between the drive strength of an NMOS component and a PMOS component ...  
WO/2019/067363A1
Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an outpu...  
WO/2019/063116A1
A signal generating system is provided. The signal generating system provides a microwave signal to a plurality of qubits. The signal generating system includes a generator, an oscillator, a mixer, and a splitter. The oscillator generate...  
WO/2018/203942A3
Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set...  
WO/2019/048919A1
The invention relates to a circuit comprising a DC-to-DC converter and an input circuit which is connected on the line side of the DC-to-DC converter and has a first terminal and a second terminal for connection to a power supply, and a ...  
WO/2019/040323A1
Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edg...  
WO/2019/040240A1
A flip-flop (100) is provided that includes a sense-amplifier-based master latch (105) clocked by a first edge of a delayed version of a clock signal (120out). A slave latch (110) includes a cross-coupled pair of logic gates for latching...  
WO/2019/040949A1
Some embodiments include a high voltage waveform generator comprising: a generator inductor; a high voltage nanosecond pulser having one or more solid state switches electrically and/or inductively coupled with the generator inductor, th...  
WO/2019/037430A1
A power supply circuit and a display device. The power supply circuit comprises: a power management integrated module (10) comprising a driving pin (11), the driving pin (11) being used for transmitting a driving signal; and a power tran...  
WO/2019/033306A1
Disclosed by the present invention are a method and apparatus for the dynamic adjustment of pulse width modulation signals: determining a target duty cycle and a number of bits of control precision; determining a number of bits for pulse...  
WO/2019/036154A1
A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circu...  
WO/2019/036179A1
A hybrid pulse-width control circuit is provided that includes a ramp voltage generator for generating a ramp voltage signal. A clock pulse generator asserts an output clock signal responsive to the ramp voltage signal equaling a referen...  
WO/2019/030667A1
Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS'), which have outputs (o-GPRS, o-GPRS') connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detecto...  
WO/2019/030669A1
Metastability based random number generator comprises an adjustable speed oscillatory response multivibrator (MOORS), having an output (Q) connected to an input (TQ) of a counter (LCZ). The output (T) of the counter (LCZ) is connected to...  
WO/2019/032085A1
Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise...  
WO/2019/030668A1
Metastability based random number generator comprises a block for metastability generation of time intervals (GMICRS') having at least two outputs (T1, T2, T3, T4, T5) and at least one speed control input (RS1, RS2, RS3, RS4, RS5), and i...  
WO/2019/032899A1
A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply "clocks") fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB...  
WO/2019/029929A1
The invention relates to a reliably operating triggerable spark gap TFS with small dimensions. The spark gap has a base BP and a cap KP. A cathode K, an anode A, and a trigger electrode TE in the form of conductive coatings are formed on...  
WO/2019/023000A1
A superconducting bidirectional current driver (10) is disclosed. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch...  
WO/2019/015724A1
The invention relates to a follow-hold circuit, for converting an analog input signal into a digital output signal, having a hold capacity unit, having a voltage amplifier unit containing an input, to which an analog input voltage signal...  
WO/2019/016530A1
A waveform generator (200) configured to generate two waveforms (211, 213) of opposite polarity so as to provide a voltage gain across a load (207). The waveform generator (200) has a primary side circuit comprising a first inductor (201...  
WO/2019/011845A1
The device comprises at least the following components : - a heating resistor (20), intended to heat a component to be regenerated; - a current source (2); - a thermistor (10), connected to the current source (2) and thermally coupled to...  
WO/2019/001769A1
The invention relates to a high-voltage semiconductor switch specifically for pulse discharges, which has a novel power supply of the active electronics system at the different reference voltage levels which result from the distribution ...  
WO/2018/236883A1
A parallel Marx generator topology capable of producing high power, high current output pulses is provided. The parallel Marx generator topology can include a plurality of Marx generators that operate in parallel to one another to jointl...  
WO/2018/230235A1
Provided are a latch circuit and a flip-flop circuit that have superior single event upset (SEU) resistence. The latch circuit according to the present invention having single event upset (SEU) resistence is configured such that, with re...  
WO/2018/226364A1
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a fi...  
WO/2018/222344A3
Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch...  
WO/2018/222344A2
Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch...  
WO/2018/215804A1
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS e...  
WO/2018/212937A1
Aspects of the disclosure are directed to a level shifter circuit (400). In accordance with one aspect, the level shifter circuit includes a high voltage device; a latch having a first side and a second side, wherein the latch is tied to...  
WO/2018/211257A1
A light pulse generating circuit is described for generating light pulses from a diode light source such as an LED or laser diode. The light pulse generating circuit comprises a charge storage device and a trigger circuit for triggering ...  
WO/2018/203943A3
Josephson transmission lines, JTLs, for superconducting devices and related methods are provided. In one example, a device (150) comprising a JTL for propagating quantum pulses in a first direction in response to an application of a cloc...  
WO/2018/199788A1
A device for generating a high pulse voltage comprises a source (1) of high direct voltage, an inductive load (9), two controllable switching devices (7) and (12), a controllable switch (41) and, connected in series, a capacitor (31), a ...  
WO/2018/193150A1
A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequen...  
WO/2018/192790A1
The oscillator circuit comprises first and second integrator units (100, 200) with a first capacitor (110) charged at a first integration node (121) and a second capacitor (210) charged at a second integration node (221). A comparator un...  
WO/2018/191080A1
A controller for use in a power converter includes a control circuit coupled to generate a low side drive signal to control switching of a low side switch, and generate an ON signal and an OFF signal in response to a feedback signal repr...  
WO/2018/190959A1
An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The l...  
WO/2018/187022A1
The disclosure relates to a data level shifter circuit (100) including a boost circuit (120+, 120-) configured to generate a boosted input data signal (VB+, Vb-) based on a transition of an input data signal (Vin+, Vin-); a first input t...  
WO/2018/176114A1
The present invention relates to a method for recovering electrical energy and to an electrical energy recovery system which uses said method for recovering electrical energy within the power grid itself, by means of an electrical circui...  
WO/2018/183874A1
Some embodiments include a high voltage, high frequency switching circuit. The switching circuit may include a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than ...  
WO/2018/182961A1
A circuit (200) including an output node (OUT) and a cross-coupled pair of semiconductor devices (204, 214) configured to provide, at the output node, an output signal in a second voltage domain (VDDH) based on an input signal in a first...  
WO/2018/178867A1
A pulsed-power circuit includes first, second, third and fourth compression stages. The first and second stages each include at least one pre-charged capacitor and at least one inductor in series, and at least one switch operative to pum...  
WO/2018/181149A1
A ring oscillator (8) comprising a plurality of logic inversion circuits (11a, 11b, 12) connected in a ring generates a multiphase clock signal. A period measurement unit (9) measures the period of a reference clock (CLK) that is input, ...  

Matches 1 - 50 out of 26,520