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Matches 1 - 50 out of 26,440

Document Document Title
WO/2018/222344A2
Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch...  
WO/2018/215804A1
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS e...  
WO/2018/212937A1
Aspects of the disclosure are directed to a level shifter circuit (400). In accordance with one aspect, the level shifter circuit includes a high voltage device; a latch having a first side and a second side, wherein the latch is tied to...  
WO/2018/211257A1
A light pulse generating circuit is described for generating light pulses from a diode light source such as an LED or laser diode. The light pulse generating circuit comprises a charge storage device and a trigger circuit for triggering ...  
WO/2018/199788A1
A device for generating a high pulse voltage comprises a source (1) of high direct voltage, an inductive load (9), two controllable switching devices (7) and (12), a controllable switch (41) and, connected in series, a capacitor (31), a ...  
WO/2018/193150A1
A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequen...  
WO/2018/192790A1
The oscillator circuit comprises first and second integrator units (100, 200) with a first capacitor (110) charged at a first integration node (121) and a second capacitor (210) charged at a second integration node (221). A comparator un...  
WO/2018/191080A1
A controller for use in a power converter includes a control circuit coupled to generate a low side drive signal to control switching of a low side switch, and generate an ON signal and an OFF signal in response to a feedback signal repr...  
WO/2018/190959A1
An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The l...  
WO/2018/187022A1
The disclosure relates to a data level shifter circuit (100) including a boost circuit (120+, 120-) configured to generate a boosted input data signal (VB+, Vb-) based on a transition of an input data signal (Vin+, Vin-); a first input t...  
WO/2018/176114A1
The present invention relates to a method for recovering electrical energy and to an electrical energy recovery system which uses said method for recovering electrical energy within the power grid itself, by means of an electrical circui...  
WO/2018/183874A1
Some embodiments include a high voltage, high frequency switching circuit. The switching circuit may include a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than ...  
WO/2018/182961A1
A circuit (200) including an output node (OUT) and a cross-coupled pair of semiconductor devices (204, 214) configured to provide, at the output node, an output signal in a second voltage domain (VDDH) based on an input signal in a first...  
WO/2018/178867A1
A pulsed-power circuit includes first, second, third and fourth compression stages. The first and second stages each include at least one pre-charged capacitor and at least one inductor in series, and at least one switch operative to pum...  
WO/2018/181149A1
A ring oscillator (8) comprising a plurality of logic inversion circuits (11a, 11b, 12) connected in a ring generates a multiphase clock signal. A period measurement unit (9) measures the period of a reference clock (CLK) that is input, ...  
WO/2018/175097A1
A latch circuit (200) includes an AND-NOR gate (210), a NAND gate (230), and a NOR gate (220). The AND-NOR gate includes a first AND-input configured to receive input data (DIN) and a second AND- input coupled to an output (A) of the NAN...  
WO/2018/171612A1
Disclosed are a digital signal generating apparatus (200) and a digital communication system. The digital signal generating apparatus (200) comprises a power supply port (204), a rectifying circuit (201) connected to the power supply por...  
WO/2018/171984A1
The invention relates to a configuration switch (1) for setting a specific configuration of a plurality of configurations that can be set. The configuration switch (1) has at least a plurality of different selectable RC combinations (2a,...  
WO/2018/164828A1
A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a freq...  
WO/2018/162456A1
A laser driver is described which comprises a resonant circuit having an inductor and a DC blocking capacitor. A biasing voltage reference is operably coupled to the inductor. A controller is operable for controlling the resonant circuit...  
WO/2018/160378A1
A master-slave level shifter array includes an asymmetric master level shifter (220A) having a predefined output state that produces an enable signal (enb) to drive an array of symmetric slave level shifters (200B) during a power collaps...  
WO/2018/160431A1
A pulse generation system is disclosed. The pulse generation system includes a controller, an output terminal, and a plurality of pulse generator circuits. The controller is configured to cause a driving signal pulse to be transmitted to...  
WO/2018/156261A1
A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit (200) for shifting a first logic domain to a second logic domain. In particular, the level shift...  
WO/2018/151541A1
A micro-pulse power supply and an electrostatic precipitator using the same are disclosed. According to one aspect of the present invention, the micro-pulse power supply applies a micro-pulse voltage to an electrostatic precipitator. The...  
WO/2018/151622A1
The invention relates to the field of high-voltage pulse technology. A generator comprises a charging circuit, a limiter and a load. The charging circuit is incorporated in a Marx generator, which also contains N1 links consisting of swi...  
WO/2018/148078A1
A device and method for generating pulses to activate and deactivate a kicker magnet is provided. When the kicker magnet is deactivated the circuit generates and stores a magnetic field in an inductor. When the kicker magnet is activated...  
WO/2018/146580A1
A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a...  
WO/2018/140353A1
An electronic component with a self-damping MLCC is provided. The electronic component comprising a pulse signal generator and a substrate comprising first traces and second traces. An MLCC is provided comprising a first capacitive coupl...  
WO/2018/137751A1
A passable latch circuit (100) and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit comprises a dynamic latch comprising a first P-transistor (MPI), a first N-transistor (MNI)...  
WO/2018/138597A1
Provided are a semiconductor device and an electronic apparatus for which power consumption has been reduced. The semiconductor device includes an encoder, a decoder, and a source driver circuit. The output terminal of the encoder is ele...  
WO/2018/133092A1
A signal processing system and a signal processing method. The signal processing system comprises: an output device (301) comprising a first positive output end and a first negative output end; a first comparator (302) comprising a secon...  
WO/2018/132131A1
The present invention includes an optimization method for an integrated circuit including multi-phase level-sensitive latches. Constraining a signal arrival time at a level-sensitive latch against the arrival time of a clock signal that ...  
WO/2018/127384A1
The invention relates to an oscillator device (1, 2) on the basis of a ring oscillator (1). Temperature-related variations in the frequency of the clock signal of a ring oscillator can be compensated by adjusting the supply voltage for t...  
WO/2018/127730A1
A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the...  
WO/2018/127726A1
A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscilla...  
WO/2018/125463A1
Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the log...  
WO/2018/122658A1
A semiconductor device comprises a lookup table comprising a memory, a first circuit and a second circuit. The first circuit receives a first signal and a second signal. The second circuit receives a third signal. When the first circuit ...  
WO/2018/115864A1
A voltage sampling circuit arrangement comprises: an oscillator circuit portion (4) arranged to produce a periodic oscillator output signal at an oscillation frequency dependent on a bias current provided thereto; a sampling circuit port...  
WO/2018/116109A1
Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW ...  
WO/2018/112302A1
A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to...  
WO/2018/108837A1
The invention relates to a method for the detection, by a receiver device, of a pulse of a signal received by said receiver device, said received signal corresponding to data emitted with a predetermined period Tc, each data item being e...  
WO/2018/110871A1
The present invention relates to a technique of compensating a frequency error of a quadrature phase relaxation oscillator. The present invention generates a signal of a desired frequency by using a resistor and a capacitor that are less...  
WO/2018/107034A1
A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the comm...  
WO/2018/106183A1
A random number generator, RNG, a method of fabricating the same, and a method of generating a random number. The RNG, comprises at least one first avalanche photodiode, APD, configured for producing "1 " events based on dark electron in...  
WO/2018/096973A1
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...  
WO/2018/096265A1
The invention relates to a power circuit switching device (1) comprising: two switching terminals (2a, 2b); a high voltage depletion mode transistor (5) and a low voltage enhancement mode transistor (6) arranged in series between the two...  
WO/2018/098052A1
Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold...  
WO/2018/092633A1
The present technology relates to an oscillation device and an oscillation method for making it possible to keep a frequency variation of a clock signal within a predetermined range without using a reference clock signal. The oscillation...  
WO/2018/093545A1
One example includes a superconducting transmission driver system (12). The system includes a latching gate stage (18) comprising at least one Josephson junction configured to switch from an off state to an oscillating voltage state to p...  
WO/2018/080737A1
Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a...  

Matches 1 - 50 out of 26,440