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Matches 1 - 50 out of 26,412

Document Document Title
WO/2018/164828A1
A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a freq...  
WO/2018/162456A1
A laser driver is described which comprises a resonant circuit having an inductor and a DC blocking capacitor. A biasing voltage reference is operably coupled to the inductor. A controller is operable for controlling the resonant circuit...  
WO/2018/160378A1
A master-slave level shifter array includes an asymmetric master level shifter (220A) having a predefined output state that produces an enable signal (enb) to drive an array of symmetric slave level shifters (200B) during a power collaps...  
WO/2018/160431A1
A pulse generation system is disclosed. The pulse generation system includes a controller, an output terminal, and a plurality of pulse generator circuits. The controller is configured to cause a driving signal pulse to be transmitted to...  
WO/2018/156261A1
A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit (200) for shifting a first logic domain to a second logic domain. In particular, the level shift...  
WO/2018/151541A1
A micro-pulse power supply and an electrostatic precipitator using the same are disclosed. According to one aspect of the present invention, the micro-pulse power supply applies a micro-pulse voltage to an electrostatic precipitator. The...  
WO/2018/151622A1
The invention relates to the field of high-voltage pulse technology. A generator comprises a charging circuit, a limiter and a load. The charging circuit is incorporated in a Marx generator, which also contains N1 links consisting of swi...  
WO/2018/148078A1
A device and method for generating pulses to activate and deactivate a kicker magnet is provided. When the kicker magnet is deactivated the circuit generates and stores a magnetic field in an inductor. When the kicker magnet is activated...  
WO/2018/146580A1
A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a...  
WO/2018/140353A1
An electronic component with a self-damping MLCC is provided. The electronic component comprising a pulse signal generator and a substrate comprising first traces and second traces. An MLCC is provided comprising a first capacitive coupl...  
WO/2018/137751A1
A passable latch circuit (100) and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit comprises a dynamic latch comprising a first P-transistor (MPI), a first N-transistor (MNI)...  
WO/2018/138597A1
Provided are a semiconductor device and an electronic apparatus for which power consumption has been reduced. The semiconductor device includes an encoder, a decoder, and a source driver circuit. The output terminal of the encoder is ele...  
WO/2018/133092A1
A signal processing system and a signal processing method. The signal processing system comprises: an output device (301) comprising a first positive output end and a first negative output end; a first comparator (302) comprising a secon...  
WO/2018/132131A1
The present invention includes an optimization method for an integrated circuit including multi-phase level-sensitive latches. Constraining a signal arrival time at a level-sensitive latch against the arrival time of a clock signal that ...  
WO/2018/127384A1
The invention relates to an oscillator device (1, 2) on the basis of a ring oscillator (1). Temperature-related variations in the frequency of the clock signal of a ring oscillator can be compensated by adjusting the supply voltage for t...  
WO/2018/127730A1
A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the...  
WO/2018/127726A1
A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscilla...  
WO/2018/125463A1
Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the log...  
WO/2018/122658A1
A semiconductor device comprises a lookup table comprising a memory, a first circuit and a second circuit. The first circuit receives a first signal and a second signal. The second circuit receives a third signal. When the first circuit ...  
WO/2018/115864A1
A voltage sampling circuit arrangement comprises: an oscillator circuit portion (4) arranged to produce a periodic oscillator output signal at an oscillation frequency dependent on a bias current provided thereto; a sampling circuit port...  
WO/2018/116109A1
Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW ...  
WO/2018/112302A1
A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to...  
WO/2018/108837A1
The invention relates to a method for the detection, by a receiver device, of a pulse of a signal received by said receiver device, said received signal corresponding to data emitted with a predetermined period Tc, each data item being e...  
WO/2018/110871A1
The present invention relates to a technique of compensating a frequency error of a quadrature phase relaxation oscillator. The present invention generates a signal of a desired frequency by using a resistor and a capacitor that are less...  
WO/2018/107034A1
A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the comm...  
WO/2018/106183A1
A random number generator, RNG, a method of fabricating the same, and a method of generating a random number. The RNG, comprises at least one first avalanche photodiode, APD, configured for producing "1 " events based on dark electron in...  
WO/2018/096973A1
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...  
WO/2018/096265A1
The invention relates to a power circuit switching device (1) comprising: two switching terminals (2a, 2b); a high voltage depletion mode transistor (5) and a low voltage enhancement mode transistor (6) arranged in series between the two...  
WO/2018/098052A1
Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold...  
WO/2018/092633A1
The present technology relates to an oscillation device and an oscillation method for making it possible to keep a frequency variation of a clock signal within a predetermined range without using a reference clock signal. The oscillation...  
WO/2018/093545A1
One example includes a superconducting transmission driver system (12). The system includes a latching gate stage (18) comprising at least one Josephson junction configured to switch from an off state to an oscillating voltage state to p...  
WO/2018/080737A1
Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a...  
WO/2018/077719A1
In an embodiment an oscillator circuit comprises a first integrator-comparator unit (100), a second integrator- comparator unit (200), and a logic circuit (300). The first integrator-comparator unit (100) is prepared to provide a first s...  
WO/2018/072672A1
A device and method for color-printing a printed circuit, and a printed circuit. The method comprises: a printing module controlling a liquid metal printing head (1) to print liquid metal wires on an original circuit substrate (5) so as ...  
WO/2018/075445A1
An electro-optical sensor chip assembly (SCA) that includes a detection device that includes an array of detector unit cells arranged in a matrix and that produce an electrical output in response to light. The SCA also includes an integr...  
WO/2018/073668A1
A technique relates to a circuit for a sum frequency generator. A first resonator is connected to a Josephson ring modulator (JRM), and the first resonator is configured to receive a first photon at a first frequency.A second resonator...  
WO/2018/071167A1
Some embodiments include a high voltage nonlinear transmission line that includes a high voltage input configured to receive electrical pulses having a first peak voltage that is greater than 5 kV having a first rise time; a plurality of...  
WO/2018/071114A1
Digital-to-analog converter (master DAC) circuitry is disclosed that is programmable to set a controlled slew rate for pulses that are otherwise defined as having sharp amplitude transitions. For example, when producing a biphasic pulse,...  
WO/2018/052513A1
Systems and methods for process variation power control in three- dimensional integrated circuits, 3DICs, are disclosed. In an exemplary aspect, at least one process variation sensor (324, 326) is placed in each tier (302) of a 3DIC (300...  
WO/2018/048052A1
The present invention relates to an operational method for a random pulse generator which uses radioisotopes. The operational method for a random pulse generator which uses radioisotopes according to the present invention comprises the s...  
WO/2018/048912A1
Current generation circuitry for an Implantable Pulse Generator (IPG) is disclosed. The IPG comprises a plurality of PDACs and NDACs for souring currents to electrode nodes. The PDACs and NDACs can be configured as pairs to each provide ...  
WO/2018/048506A1
An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of...  
WO/2018/048572A1
Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal...  
WO/2018/044563A1
One example includes an isochronous receiver system. The system includes a single flux quantum (SFQ) receiver configured to receive a data signal from a transmission line and to convert the data signal to an SFQ signal. The system also i...  
WO/2018/044562A2
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/044562A3
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/045223A1
In described examples, an apparatus (200) includes: a capacitor (230) having a first terminal coupled to receive a current and having a second terminal coupled to a ground; a first comparator (240) coupled to a voltage at the first termi...  
WO/2018/044383A1
A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered thr...  
WO/2018/044665A1
One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic oper...  
WO/2018/038854A1
An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coup...  

Matches 1 - 50 out of 26,412