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WO/2018/234309A1 |
A avalanche diode arrangement comprises an avalanche diode (11) that is coupled to a first voltage terminal (14) and to a first node (15), a latch comparator (12) with a first input (16) coupled to the first node (15), a second input (17...
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WO/2018/235373A1 |
The comparator with hysteresis is provided with: a comparator (110) for alternately switching between a first threshold value and a second threshold value smaller than the first threshold value in accordance with an input signal, compari...
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WO/2018/232002A1 |
Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signal...
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WO/2018/230338A1 |
The present technique relates to a clock enabler circuit capable of preventing a whisker from occurring in an output clock. A gate signal generation unit generates an input clock-enabling gate signal on the basis of an input clock and an...
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WO/2018/229610A1 |
A system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circ...
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WO/2018/224553A1 |
The invention relates to a charge controller (10) for controlling a charging process of an electric vehicle (80). In order to achieve an improved charge controller (10), in particular for improved communication of the charge controller (...
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WO/2018/226364A1 |
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a fi...
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WO/2018/220569A1 |
Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes...
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WO/2018/220470A1 |
Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The com...
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WO/2018/215334A1 |
A method for wideband generation of IQ signals involves a reference signal initially having its frequency doubled and subsequently being supplied to a master-slave D-type flip-flop (DIV2) in order to obtain an I component and a Q compone...
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WO/2018/216677A1 |
Provided is a comparison circuit from which a comparison result can be output without providing a half-latch circuit in a subsequent-stage logic circuit operating with the same clock as for the comparison circuit, and with which a decrea...
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WO/2018/217786A1 |
Methods and systems are described for obtaining, at an input stage of a sampler, a continuous-time analog differential voltage, and responsively generating an integrated analog differential voltage by discharging a pair of pre-charged ou...
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WO/2018/212937A1 |
Aspects of the disclosure are directed to a level shifter circuit (400). In accordance with one aspect, the level shifter circuit includes a high voltage device; a latch having a first side and a second side, wherein the latch is tied to...
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WO/2018/206708A1 |
The invention relates to a signal processing device for high-precision measuring of the transit time of two signals, in particular a measuring device for high-precision measuring of the transit time of at least two digital signals. The a...
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WO/2018/203149A1 |
A StrongARM latch comparator (500) includes first and second p-type metal- oxide-semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n- type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), where...
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WO/2018/200843A1 |
In methods and apparatus for detecting zero-volt crossing in a field-effect transistor, a comparator (200) compares a drain-to source voltage (Vds) of the transistor to a threshold voltage (VTH-ds). A gate voltage signal (Vgs) of the tra...
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WO/2018/194902A1 |
A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor s...
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WO/2018/194538A1 |
A zero cross detection circuit is included in a system circuit for accurately detecting a zero cross event from an alternating current power source in the system circuit. The detecting zero cross event is monitored to accurately time a c...
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WO/2018/194753A1 |
Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that th...
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WO/2018/188127A1 |
Disclosed is a storage interface. The storage interface is connected between a main controller and a storage device, and may comprise: a first programmable input/output unit, used for performing phase inversion on a clock signal output b...
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WO/2018/189288A1 |
An asynchronous state machine (30) for a phase/frequency detector (12) operative in a phase locked loop (10) includes a short pulse suppression circuit (40, 50, 60, 70, 80) operative to suppress output pulses of duration on the order of ...
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WO/2018/179920A1 |
[Problem] To control delay time with high accuracy. [Solution] A delayed locked loop circuit provided with: a first delay circuit that comprises at least one first delay device and at least one second delay device, the first delay device...
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WO/2018/182585A1 |
A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase ...
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WO/2018/181149A1 |
A ring oscillator (8) comprising a plurality of logic inversion circuits (11a, 11b, 12) connected in a ring generates a multiphase clock signal. A period measurement unit (9) measures the period of a reference clock (CLK) that is input, ...
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WO/2018/180022A1 |
[Problem] To provide a pulse position modulation circuit capable of suppressing variations in delay time. [Solution] This pulse position modulation circuit is provided with: a delay path that comprises a plurality of delay devices connec...
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WO/2018/166130A1 |
Disclosed are a duty cycle adjustment apparatus and method. The apparatus comprises: a first edge extraction unit (1) for extracting a rising edge of a first clock signal; a lock determination unit (2), with an input end connected to the...
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WO/2018/164818A1 |
Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature ("PVT") and input common mode (Vcm) variations. This can be accomplished by separating and then varying...
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WO/2018/161083A1 |
In described examples, clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock (100) with active and inactive clock edges (101, 102) within a clock period (TCLOCK), and signal ca...
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WO/2018/159343A1 |
Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a re...
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WO/2018/160578A1 |
Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a powe...
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WO/2018/150184A1 |
A duty cycle conversion circuit portion (1) comprises N inverters (2, 4, 6, 8), wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals (10a-d) each having a duty cycle between 1...
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WO/2018/144413A1 |
Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direct...
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WO/2018/141878A1 |
A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality ...
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WO/2018/144126A1 |
An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by ...
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WO/2018/137751A1 |
A passable latch circuit (100) and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit comprises a dynamic latch comprising a first P-transistor (MPI), a first N-transistor (MNI)...
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WO/2018/136151A1 |
In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed vers...
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WO/2018/127721A1 |
A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents...
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WO/2018/127730A1 |
A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the...
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WO/2018/121469A1 |
Disclosed in the present invention are a system and a method for high-precision clock delay calibration. The calibration system comprises a NAND gate, an AND gate, a time delay chip, a multiplexer and a processing module; the multiplexer...
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WO/2018/125489A1 |
A proximity detector circuit that receives a single-ended sensor signal includes (a) an adaptive level control circuit maintaining the single-ended sensor signal within a predetermined voltage range relative a common mode reference signa...
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WO/2018/120555A1 |
The present invention discloses a phase interpolator circuit and a method for improving the linearity thereof, the phase interpolator circuit comprising: N phase interpolator units, N≥2; a phase interpolator unit comprises a differenti...
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WO/2018/118274A1 |
A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference sign...
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WO/2018/116109A1 |
Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW ...
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WO/2018/119081A1 |
An output clock frequency (102, 202, 850) of an adaptive oscillator circuit (120, 200, 800, 1000) changes in response to noise on an integrated circuit power supply line (220, 820). The circuit features two identical delay lines (210, 81...
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WO/2018/112302A1 |
A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to...
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WO/2018/107034A1 |
A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the comm...
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WO/2018/096973A1 |
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...
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WO/2018/090650A1 |
The invention discloses a clock compensation circuit, a clock circuit, and a microcontroller. The clock compensation circuit comprises: a detection circuit used to detect a capacitance control parameter capable of affecting a clock frequ...
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WO/2018/087914A1 |
The present invention is configured so as to comprise: a high-pass filter (2) that eliminates an offset included in an AC signal Vin input from a signal input terminal (1); and a waveform restoration unit (3) that, using a time constant ...
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WO/2018/087187A1 |
The invention relates to a method for transferring target values (S) by means of target value signals and parameterization values (P) by means of parameterization signals for parameterizing an electric motor, in particular an EC motor vi...
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