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WO/2017/151260A1 |
A pulse generator discharge circuit is disclosed. The circuit includes one or more discharge stages, each discharge stage including a plurality of control input terminals. The circuit also includes first and second discharge terminals, a...
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WO/2017/149956A1 |
This signal output circuit (1, 51) comprises a slope control circuit (6), a capacitor (9), a noise detection circuit (14, 31, 41) and a malfunction prevention circuit (7). The slope control circuit charges and discharges the capacitor, t...
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WO/2017/145392A1 |
The purpose of the present invention is to provide an electrical apparatus allowing a drastic reduction in the number of contact input terminals. An electric apparatus 3 is equipped with an input device 1 that receives an analog signal. ...
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WO/2017/144235A1 |
The invention relates to a communication interface between a control unit and an electric load unit, particularly a load unit having a pump motor in a motor vehicle, wherein the control unit is designed as a transmitter and/or receiver, ...
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WO/2017/143315A1 |
An embodiment in accordance with the present invention provides a system and method of physically modulating a digital signal across a medium. A signal is sent one bit at a time (serially) as a period of high voltage followed by a period...
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WO/2017/142696A1 |
The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The firs...
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WO/2017/136052A2 |
A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated...
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WO/2017/131844A1 |
A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs (121) coupled to receive a plurality of clock signals; a plurality of transistor pa...
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WO/2017/131934A1 |
The present disclosure is directed to methods and systems for providing information about a target based on pulse widths. The information can be provided in a formatted output signal which uses a pulse width protocol to code information ...
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WO/2017/123269A1 |
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devic...
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WO/2017/119488A1 |
A serializer device 1 is provided with a first latch unit 11, a second latch unit 12, a conversion unit 13, a frequency division unit 14, a load signal generation unit 15, a phase difference detection unit 16, and a reset indication unit...
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WO/2017/119220A1 |
In order to simplify a comparison device of an analog-to-digital conversion apparatus, in the comparison device, an input signal is input to control terminals of a plurality of signal input transistors. A reference input transistor forms...
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WO/2017/112222A1 |
An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.
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WO/2017/108264A1 |
The invention relates to a method and an apparatus (1) with a circuit arrangement (3) comprising at least one mechanical switch (5) which is used to open and/or close an electrical contact (7), and a processor unit (9) which is used to c...
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WO/2017/101167A1 |
A controllable splitting method for a large current pulse and an apparatus therefor. The method comprises: electrically connecting a silicon carbide photo-conductive switch between input and output ends of a current pulse; connecting a t...
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WO/2017/100666A1 |
A wireless communication method includes generating a pilot signal that is represented using a complex exponential signal having a first linear phase in a time dimension and a second linear phase in a frequency dimension; and transmittin...
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WO/2017/098624A1 |
A semiconductor device driving circuit is provided with: a signal transmission circuit including a first level shift circuit for level-shifting an input signal having a first voltage level and generating, on the basis of the input signal...
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WO/2017/096766A1 |
A method and device for eliminating interference and a smart television set. The method comprises: determining whether an interference pulse exists in a current inter-integrated circuit (IIC) bus when sensing a read/write data instructio...
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WO/2017/094310A1 |
The present invention improves the operating range of a phase detector equipped with flip-flops and improves the jitter resistance of a reception circuit. This phase detector is provided with a retention unit and a detection unit. In the...
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WO/2017/095601A1 |
Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to t...
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WO/2017/080925A1 |
In a data processing architecture comprising a control unit and converters CNj to be synchronised on an active edge of a common reference clock CLK, a synchronisation method involves the arrangement of the converters into at least one se...
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WO/2017/075296A1 |
A dual stage power converter capable of being installing in a one-gang box and powering an LED load is presented. The dual stage converter can include a power factor correction (PFC) stage operating in transition mode and a resonant conv...
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WO/2017/068035A1 |
Signal processing method for histogram generation, and corresponding device and use. A signal processing method for histogram generation from a plurality of event detectors, that generate event signals as a response to external events, a...
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WO/2017/064076A1 |
Disclosed is a method for controlling a semiconductor switch (HS) using a pulse-width-modulated control signal (PWM). A check is made (S100) to determine whether a current duty cycle (Tm) of the control signal (PWM) lies within a duty cy...
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WO/2017/051654A1 |
A ringing suppression circuit that is connected to a transmission line for transmitting a differential signal changing between binary levels of High and Low by means of a pair of high and low potential side signal lines and that suppress...
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WO/2017/049989A1 |
A high speed low power consumption dynamic comparer, comprising a latch, an AND gate, a delay unit, and an XNOR gate. The latch has first to third control terminals. Outputs of the latch pass through inverters I1 and I2 respectively to p...
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WO/2017/052876A1 |
A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a m...
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WO/2017/046073A1 |
A voltage comparator (1) has a high switching speed and simplicity of design. It minimizes pulse-width distortion of input digital signals when functioning as a digital input buffer in high speed communications applications. In addition ...
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WO/2017/039852A1 |
Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a ris...
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WO/2017/039984A1 |
Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that i...
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WO/2017/038592A1 |
This ringing suppression circuit is connected to a transmission line (3) for transmitting a differential signal that changes into two value levels, high and low, by a pair of signal lines, and suppresses ringing which is produced along w...
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WO/2017/031575A1 |
An optoelectronic oscillator (OEO) is disclosed comprising an electronically tunable filter for transposing narrow pass band characteristics of a surface acoustic wave (SAW) filter to a microwave frequency to provide mode selection in th...
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WO/2017/030726A1 |
An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a sec...
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WO/2017/029484A1 |
A delay measurement apparatus for measuring a delay unit comprising: a clock; clock counter that counts clock cycles; a digital signal source that is uncorrelated with the clock; a first detector arranged to detect transitions of the dig...
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WO/2017/029774A1 |
This signal transmission circuit is provided with: a primary element into which a differential signal generated from a transmission signal and having an alternating-current component is input; a secondary element that is magnetically or ...
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WO/2017/025619A1 |
The invention relates to a device for detecting signal pulses (2) in an analog measuring signal (1) of a particle counter. Said device comprises an AD converter (6) and an evaluation unit (10) that includes a slope evaluation unit (16) w...
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WO/2017/027157A1 |
A particular apparatus (100) includes a magnetic tunnel junction (MTJ) device (102) and a transistor (120). The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition...
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WO/2017/025202A1 |
Circuit assembly for protecting a unit to be operated from a supply network against surges, comprising an input having a first and a second input connection, which are connected to the supply network, an output to which the unit to be pr...
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WO/2017/021013A1 |
The invention relates to a circuit assembly for protecting a unit to be operated from a supply network against overvoltage, comprising an input having a first and a second input connection, which are connected to the supply network, an o...
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WO/2017/019365A1 |
Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry (100) is made simpler ...
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WO/2017/016242A1 |
A clock delay circuit, comprising: a control module (102) and at least one stage of delay module (101). The delay module (101) is configured to perform a delay. Two output terminals of each stage of the delay module (101) are respectivel...
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WO/2017/019219A1 |
An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to generate a first signal in response to a clock signal. The apparatus further includes a delay circuit of the CGC. The delay circuit is configured t...
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WO/2017/019290A1 |
A method and receiver for detecting a signal wherein the signal is encoded the signal with a pair of spaced predetermined frequencies and wherein energy is detected in each of the pair of predetermined frequencies and in a predetermined ...
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WO/2017/011479A1 |
A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit (302) having a first current path (325) for receiving a first input signal (Dataln) of...
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WO/2017/005863A1 |
The present invention relates to a single phase, non-insulated, miniaturized DC/AC power inverter (1) having an output power density higher than 3000 W/dm³, wherein said first (S1_H), second (S1_L), third (S2_H) and fourth(S2_L)switches...
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WO/2016/210276A1 |
Method and apparatus to produce a step function with a designed transition (rise and/or fall) time on the order of <10ns that reaches steady state by implementing a system that sums a number of currents at different rise times (frequenci...
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WO/2016/204912A1 |
Described herein are methods and subsystems for use with a timing generator having an output driver at which a timing signal having timing pulses is output. A method includes controlling the timing generator to cause the output driver to...
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WO/2016/202896A1 |
The method is used for transmitting signals and data during at least one first and one second transmission phase (TP1, TP2), which follow one another synchronously or asynchronously, between a first communication unit (L) and at least on...
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WO/2016/203491A2 |
The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock networ...
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WO/2016/204962A1 |
Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for bet...
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