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WO/2021/261229A1 |
The light detection device according to the present invention is provided with: a pixel capable of generating a pixel signal; a reference signal generating unit capable of generating a reference signal; a comparison circuit including a f...
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WO/2021/249759A1 |
Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can ...
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WO/2021/251305A1 |
[Problem] To detect gain mismatch. [Solution] This comparator is provided with: a first comparison circuit which compares a first differential input signal pair; a second comparison circuit which compares a second differential input sign...
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WO/2021/243451A1 |
Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurem...
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WO/2021/247820A1 |
An apparatus for ion manipulation having improved duty cycle includes first and second separation regions separated by a switch that alternates between guiding ions to each of the separation regions. The separation regions separate the i...
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WO/2021/237288A1 |
Described herein is a pulse detection circuit (1402, 1500, 1600, 1700) configured to detect peak pulse values from pulses contained in an input analog signal (126). The circuit includes a control circuit (1502) to generate a peak control...
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WO/2021/243019A1 |
An analog to digital conversion (ADC) circuit includes a voltage-controlled oscillator (VCO)-based quantizer that receives a voltage input signal to be quantized and provides a digital output. A predictor samples the digital output, eval...
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WO/2021/230446A1 |
According to an embodiment, provided is a vacuum cleaner having: a body which has a power part for supplying power, a first motor for generating a suction force and a first PCB having a first control part mounted thereon; and a nozzle wh...
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WO/2021/231026A1 |
Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuratio...
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WO/2021/228480A1 |
A comparator circuit comprises an input stage with a set of differential current paths and a pair of differential input transistors (N1, N2; P7, P8) connected to a pair of input terminals (INN, INP). An output stage comprises an output c...
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WO/2021/228889A1 |
A time delay circuit comprising a plurality of differential delay cells 8 each having a respective time delay and being arranged in series. Each delay cell 8 comprises first and second inverter sub-cells 2a, 2b, each comprising a respect...
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WO/2021/219304A1 |
Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse ge...
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WO/2021/203875A1 |
Embodiments of the present application relate to the technical field of circuits, and provide a pulse elimination circuit, and a voltage measurement circuit and a measurement method. The pulse elimination circuit comprises: a clock gener...
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WO/2021/206751A1 |
A voltage comparator and a programmable counter coupled to a high-speed clock are used to provide a near constant delay time for use in a closed-loop system. The voltage comparator input-output time delay is characterized at a certain te...
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WO/2021/204522A1 |
The peak comparator circuitry (1) comprises a differential amplifier circuit (100) having an output node (O100) to generate a differential amplifier output signal (Out1) in response to an amplification of a difference of an input signal ...
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WO/2021/199955A1 |
A pulse edge detection circuit 7, wherein in a measurement circuit 4, an internal comparator compares a voltage Vds with a reference voltage and outputs a pulse signal Vin. An RSFF 11 sets a signal OUT1 to a high level at the timing at w...
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WO/2021/199682A1 |
A mirror clamp circuit according to the present invention has: a comparator having a first input terminal that can be connected to a first control terminal of a transistor and a second input terminal to which a reference voltage is appli...
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WO/2021/202451A1 |
Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector, PFD, (3110) which outputs differential error clocks based on comparison of differential reference clocks and differen...
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WO/2021/200415A1 |
[Problem] To prevent an input voltage-dependent error due to input parasitic capacitance. [Solution] This comparator comprises: a first transistor and a second transistor having two interconnected sources, two gates to which a differenti...
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WO/2021/200416A1 |
[Problem] To suppress kickback currents, and to prevent deviations in a signal for outputting a comparison result. [Solution] This comparator comprises: a first input terminal and a second input terminal into which a first pair of differ...
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WO/2021/199683A1 |
Provided is a comparator circuit comprising: a first comparator that receives input of an input signal and a comparison target signal to be compared with the input signal; a first output stage that includes an N-channel transistor having...
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WO/2021/187183A1 |
This comparison circuit is provided with: a first comparator configured to compare a voltage based on an input voltage with a first reference voltage; a charging and discharging unit configured to switch between charging and discharging ...
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WO/2021/183255A1 |
Signals sent to a memory component are received by circuitry included in the memory component. The circuitry comprises a comparator circuit to process the received signals. The circuitry further comprises a resistor-capacitor (RC) circui...
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WO/2021/181857A1 |
The purpose of the present invention is to make a delay correction circuit more compact. This delay correction circuit is provided with a standard delay circuit, a phase comparator, a delay adjustment unit, and a standard delay circuit...
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WO/2021/183915A1 |
In certain examples, methods and semiconductor structures are directed to circuit-based apparatus in which an amplifier includes stacked, first and second circuit amplification stages to operate out of phase from one another for providin...
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WO/2021/168866A1 |
An anti-interference distance measuring device and method. The device comprises a pulse position modulator (1011) and a phase-shift keying modulator (1012) connected to the pulse position modulator (1011). The pulse position modulator (1...
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WO/2021/168552A1 |
A "frequency shifter" is a clock synthesis system, that includes either a multiplexer or a multi- modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchroni...
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WO/2021/165565A1 |
In a microelectronic circuit, a digital value (D) is temporarily stored in a register circuit (101). In relation to an allowable time limit defined by a triggering signal (CKP), there is stored a corresponding momentary value of said dig...
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WO/2021/156545A1 |
A control arrangement is disclosed for providing a plurality of phase-coherent oscillating signals. It comprises a reference clock signal arrangement for providing a high-frequency reference clock signal and a plurality of modules (130) ...
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WO/2021/152938A1 |
The present invention suppresses an unnecessary circuit operation caused by a toggle operation of a clock signal in a clock enabler circuit. A state holding unit performs a holding operation of a state of whether an output clock signal...
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WO/2021/148631A1 |
Disclosed is a device (1) capable of processing a pilot control signal (CP) having at least two modes, i.e. continuous or PWM alternating, and generating a binary detection signal (SD), the state of which is an indication of the mode, th...
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WO/2021/149506A1 |
Provided is a time measurement device comprising: a first counter unit (204) that, by counting on the basis of a reference clock signal, acquires a difference time between a first signal to be measured and a second signal to be measured ...
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WO/2021/150762A1 |
Certain aspects of the present disclosure generally relate to a power stage (100). The power stage generally includes a first transistor (122), a second transistor (120) having a drain coupled to a drain of the first transistor, a first ...
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WO/2021/145970A1 |
In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and...
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WO/2021/141008A1 |
Provided are a communication device, an industrial machine, and a communication method that contribute to accurate evaluation of communication quality. The present invention comprises: a reception unit (104) that receives a serial signal...
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WO/2021/139746A1 |
A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequ...
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WO/2021/138730A1 |
A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillato...
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WO/2021/135102A1 |
Provided are a clock generation circuit and a latch using same, and a computing device. The cock generation circuit comprises an input end, used for inputting a pulse signal (CKI); a first output end, for outputting a first clock signal ...
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WO/2021/127772A1 |
A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last...
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WO/2021/129050A1 |
Provided in the present application is a glitch-free clock switching circuit, comprising: a clock selection signal generating circuit, a synchronization circuit, and a multipath selector. The clock selection signal generating circuit is ...
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WO/2021/131847A1 |
A signal processing device according to an embodiment of the present invention is provided with a first generation unit and a second generation unit. The first generation unit generates corrected data by correcting input data on the basi...
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WO/2021/126309A1 |
A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when an interpolator rollover event of a phase integer portion of a phase interpolator has occurred, an...
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WO/2021/126405A1 |
An apparatus (20) and method for synchronizing a triggered system (System B) to a triggering system (System A) by tracking the timing of rising and falling edges of a clock signal (CLK_IN) at the triggered system and using the tracked ti...
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WO/2021/126373A1 |
A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of a...
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WO/2021/122138A1 |
A duty cycle correction circuit comprises a buffer stage (120) which outputs a digital output signal (VOUT_RX) having a duty cycle. At least one buffer (125) of the buffer stage (120) is configured to exhibit a controllable tripping thre...
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WO/2021/115500A1 |
The device for accurate measurement of time intervals comprises a first comparator (1) to the input of which a first signal (STA) is fed and the output of which is connected to the first of the inputs of the combiner (3), to the second i...
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WO/2021/113887A1 |
The invention relates to a method for generating random numbers, wherein a) a source (1) emits energy, in particular in the form of pulses, with a specified distribution at non-predictable points in time, b) a detector (3) which is conne...
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WO/2021/113968A1 |
Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a...
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WO/2021/118030A1 |
The present invention relates to a low power comparator that is useful in fields, such as that of the Internet of Things, for which the importance of power conversion efficiency is increasing, the low power comparator comprising: an inpu...
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WO/2021/110043A1 |
Disclosed are a signal shaping circuit and a corresponding gate drive circuit. An additional NMOS transistor is added to the signal shaping circuit, thereby improving the requirements for the amplitude of an input differential signal, wi...
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