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Matches 1 - 50 out of 37,699

Document Document Title
WO/2018/107034A1
A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the comm...  
WO/2018/096973A1
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...  
WO/2018/090650A1
The invention discloses a clock compensation circuit, a clock circuit, and a microcontroller. The clock compensation circuit comprises: a detection circuit used to detect a capacitance control parameter capable of affecting a clock frequ...  
WO/2018/087914A1
The present invention is configured so as to comprise: a high-pass filter (2) that eliminates an offset included in an AC signal Vin input from a signal input terminal (1); and a waveform restoration unit (3) that, using a time constant ...  
WO/2018/087187A1
The invention relates to a method for transferring target values (S) by means of target value signals and parameterization values (P) by means of parameterization signals for parameterizing an electric motor, in particular an EC motor vi...  
WO/2018/089121A2
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/081883A1
Method and implementation of a detector of rapid pulses in the power supply voltage of integrated circuits, which involves conditioning the rapid pulse applied to the power supply voltage to trigger the security alarm, more specifically ...  
WO/2018/083893A1
The present invention improves the detection accuracy of a timing error in a semiconductor integrated circuit provided with a storage element that operates in synchronization with a clock signal. A delay unit delays a data signal by two ...  
WO/2018/074251A1
The present technology relates to a signal processing device, a signal processing method, and a program which enable the reduction of the effect of crosstalk. Provided are a plurality of comparators, a delay unit which delays outputs fro...  
WO/2018/073562A1
An apparatus for synchronizing an input signal (D) that is asynchronous to a clock signal (CLK) received by the apparatus. The apparatus comprising selection circuitry (104) configured to select the input signal and to generate a pair of...  
WO/2018/068330A1
Provided are a rectification circuit and a rectifier, relating to the field of electronic technologies and capable of operating normally when a voltage of an AC signal input to the rectification circuit is less than Vth. The rectificatio...  
WO/2018/071153A2
Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit gener...  
WO/2018/071167A1
Some embodiments include a high voltage nonlinear transmission line that includes a high voltage input configured to receive electrical pulses having a first peak voltage that is greater than 5 kV having a first rise time; a plurality of...  
WO/2018/071114A1
Digital-to-analog converter (master DAC) circuitry is disclosed that is programmable to set a controlled slew rate for pulses that are otherwise defined as having sharp amplitude transitions. For example, when producing a biphasic pulse,...  
WO/2018/071153A3
Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit gener...  
WO/2018/068847A1
The present invention relates to an apparatus and method for generating an analog output voltage perfectly linear according to the digital input code associated with a capacitor array DAC. An array of n capacitors is split into a first a...  
WO/2018/069046A1
The invention relates to a method for recognizing a bouncing motion of a pedal (24), comprising recognizing a restoration of the pedal (24) into an idle position (18) and detecting the occurrence of the bouncing motion of the pedal (24) ...  
WO/2018/058915A1
Disclosed is a clock signal loss detection device, comprising: a first delay unit, a second delay unit, a D flip-flop, a first NOT gate, a second NOT gate, and an AND gate. An input end of the first delay unit, a clock end of the D flip-...  
WO/2018/055149A1
The invention relates to a device (210) which includes: an analysis module (220) generating a binary signal (d(t)) for pulse detection in an incident pulse signal (s(t)); a multiplier (221) weighting the incident pulse signal (s(t)) by t...  
WO/2018/054038A1
A protection circuit of a bidirectional converter (13) and a power consumption system having a power-storage function. The protection circuit is applied to a power consumption system having a power-storage function, and comprises: a sing...  
WO/2018/057350A1
Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals ...  
WO/2018/051388A1
[Problem] To provide an analog circuit for use in a position indicator, which is of low power consumption and of high noise-resistance. [Solution] An analog circuit 90 according to the present invention is connected to an electrode 21 th...  
WO/2018/052982A2
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may...  
WO/2018/050798A1
The invention relates to a signal processing device for the highly precise measurement of the delay time of two signals. The aim of the invention is to provide a signal processing device and a measuring device for the highly precise meas...  
WO/2018/052982A3
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may...  
WO/2018/048912A1
Current generation circuitry for an Implantable Pulse Generator (IPG) is disclosed. The IPG comprises a plurality of PDACs and NDACs for souring currents to electrode nodes. The PDACs and NDACs can be configured as pairs to each provide ...  
WO/2018/045770A1
A control circuit (100, 400, 903), a control method, and an electronic device (900). The control circuit (100, 400, 903) comprises: a first control sub-circuit (101,401), which is configured to receive a first power signal (VDD1) from a ...  
WO/2018/044725A1
A transition glitch suppression circuit (400) can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal (402). The transition glitch suppression circuit has a delay element (404)...  
WO/2018/044665A1
One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic oper...  
WO/2018/038921A1
Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is prov...  
WO/2018/037946A1
This technology relates to a correcting device which makes it possible to carry out duty correction with reduced power consumption. This correcting device is provided with: a converting portion which converts an input clock into a prescr...  
WO/2018/037901A1
The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method with which it is possible to reduce the power consumption while improving the determi...  
WO/2018/023919A1
A high-power adjustable high-frequency fractional order capacitor having an order greater than 1 and a control method thereof. The fractional order capacitor comprises an alternating current input module (1), a coupling impedance (2), a ...  
WO/2018/017189A1
Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming op...  
WO/2018/017292A1
An apparatus for setting the timing of a triggering edge of a clock signal with respect to received parallel data. The apparatus includes a set of flip-flops including respective data inputs, respective clock inputs, and respective data ...  
WO/2018/012083A1
The present invention reduces a leak current while reducing low-frequency noise in an AGC circuit provided with a transistor that shifts to an on state or an off state according to the level of a signal. A switching circuit is provided w...  
WO/2018/010156A1
An electronic chip signal modulation method and system, the method comprising the following steps: obtaining signal information of an electronic chip (101); processing the signal information to obtain a peak value of the signal informati...  
WO/2018/008140A1
A pulse-width correction circuit (1) comprising: a fixing unit (10) that fixes an output signal S_OUT at a high level if, after a state in which the output signal S_OUT is low-level has continued for a first period of time, an input sign...  
WO/2018/001701A1
A driving circuit (10)to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10).In a first operating state/pre-ch...  
WO/2018/000330A1
A method and system for preprocessing a signal of an electronic chip. The method comprises the following steps: sampling signal data of an electronic chip (101); analyzing and processing the sampled data to acquire the rate of change of ...  
WO/2018/000839A1
A new on-line monitoring unit for an ultra-wide voltage and a control circuit therefor. Compared with an ordinary on-line monitoring unit, it is not necessary to reserve a delay unit to replace an original trigger in the ordinary on-line...  
WO/2017/222620A1
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...  
WO/2017/217139A1
Provided is a chattering removal circuit with which it is possible to improve the response of an output signal to variations in an input signal, at low cost and using a simple configuration. A chattering removal circuit (30) removes chat...  
WO/2017/219039A1
In described examples of a communication system (10), the system (10) includes a data transmitter (12) configured to generate a digital communication signal and a data receiver (14) configured to receive the digital communication signal....  
WO/2017/212699A1
The purpose of the present invention is to provide a sensor array device which accurately and rapidly determines and outputs data detected by a sensor. A sensor array device is provided with a sensor, and a comparison unit which compares...  
WO/2017/203624A1
The purpose of the present invention is to achieve size reduction and simplification of the circuit configuration of an intelligent power module (IPM) through phase synchronization of the IPM. The IPM pertaining to the present invention ...  
WO/2017/199790A1
In a monitor circuit (10), a data signal (D1) is propagated from an FF (11) to an FF (12) via a data delay circuit (16). The data delay circuit (16) selects, in accordance with a selection signal (TN1), any one from among data paths (161...  
WO/2017/197946A1
Disclosed is a PVTM-based, wide-voltage-range clock stretching circuit. The circuit comprises a PVTM circuit module, a phase clock generation module, a clock synchronization selection module, and a control module. The PVTM circuit module...  
WO/2017/195615A1
The present technology relates to a detection device and a detection method that enable a lock state to be determined more accurately. A first edge detector detects whether an edge of a second clock signal is present in one cycle of a fi...  
WO/2017/190948A1
The invention relates to an integrated semiconductor circuit (10) comprising at least one input terminal (12; 12_1 to 12_E'). A debouncing device (14) that is integrated into the semiconductor circuit in order to debounce an input signal...  

Matches 1 - 50 out of 37,699