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Matches 1 - 50 out of 37,936

Document Document Title
WO/2019/093312A1
A measurement unit (3) generates, at every period of a reference clock, a period measured value representing the period of the reference clock as a number of passage stages, which is the number of stages at which a circulating signal pas...  
WO/2019/091110A1
The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive data samples of the received data signal a...  
WO/2019/022825A3
An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling...  
WO/2019/092440A1
A circuit portion (100) is provided which comprises a phase expansion portion (111) arranged to receive an oscillating input signal (202) with a first frequency and output a first digital signal (206) having a plurality of parts each hav...  
WO/2019/079116A1
A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock inpu...  
WO/2019/079030A1
A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits (304i, 3042) that output in-phase and anti-in-phase clock signals (cki, cki_b), respectively, of a four-phase clock signal (122); a second pa...  
WO/2019/073840A1
A sequence circuit 1 comprises: a detection unit (2) that detects the occurrence of an event on the basis of an input signal; an acceptance unit (4) that accepts the event the occurrence of which has been detected by the detection unit; ...  
WO/2019/074708A1
Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An inpu...  
WO/2019/074727A1
An example digital-to-time converter (DTC) (102) includes: a delay chain circuit (301) having a plurality of delay cells (302) coupled in sequence, the delay chain circuit including a first input (Fref) to receive a first clock signal an...  
WO/2019/068465A1
The invention relates to a method for monitoring a sensor clock signal (STS) in a sensor unit (10), which is generated and output for a data transfer between the sensor unit (10) and a control unit with a predefined period duration, wher...  
WO/2019/070196A1
Various embodiments may relate to a clocking circuit arrangement. The clocking circuit arrangement may include a clock source, as well as a global monitoring circuit arrangement including a monitoring tunable clock buffer, a reference cl...  
WO/2019/068460A1
The invention relates to a method for correcting at least one transmission parameter for data transmission between a sensor unit (10) and a control unit, wherein a sensor timing signal (STS) is generated by a sensor oscillator (14) with ...  
WO/2019/063117A1
Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes th...  
WO/2019/066157A1
In order to minimize a popping noise generated in a pest extermination device that outputs high frequencies at different pitches by varying the frequencies over time or in a mobile terminal provided with the pest extermination device, a ...  
WO/2019/061077A1
A pulse width modification circuit, pulse width modification method, and electronic apparatus, configured to solve an existing problem in which a pulse width of a clock signal received by a digital clock does not meet a requirement. The ...  
WO/2019/054981A1
Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency incl...  
WO/2019/049320A1
Provided is a signal output device capable of appropriately outputting a signal even when a received signal amount is low. A signal output device 1 is provided with: a high-side comparator 30; a low-side comparator 40; a high-side AC cou...  
WO/2019/046442A1
For producing a low-power, low-phase noise oscillating signal, using an oscillator (102), a signal is produced having a base frequency component and an Nth harmonic component (112). N is a selected integer, and N > 1. The signal is filte...  
WO/2019/029890A1
According to the invention, an input stage (50) for an LVDS receiver circuit (100) is provided, comprising at least one supply voltage connection (41) and a first and a second stage input (11, 12) for applying a differential input signal...  
WO/2019/030080A1
The invention relates to a transceiver (12; 120; 1200) for a bus system (1) and to a method for reducing an oscillation inclination upon transitioning between different bit states. The transceiver (12; 20; 1200) has a first driver (1211)...  
WO/2019/029819A1
An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50 j...  
WO/2019/028595A1
An oscillator, an integrated circuit, a timing chip, and an electronic device. The oscillator comprises a bias circuit (100) and a current mode comparator (200). The bias circuit (100) is connected to the current mode comparator (200). T...  
WO/2019/030081A1
The invention relates to a transceiver (12; 120) for a bus system (1) and to a method for reducing an oscillation inclination upon transitioning between different bit states. The transceiver (12; 120) has a first driver (123, 124, 125) f...  
WO/2019/028335A1
An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding ...  
WO/2019/022905A1
Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system (100) includes a first receive path (110) configured to directly sample a first signal in a first frequency range. The system (100)...  
WO/2019/022825A2
An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling...  
WO/2019/009968A1
A quarter-rate clock signal (205 out) is doubled in a frequency doubler (210, 220, 235) to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface (215, 240) to serialize (215) and deserialize (240) data (25...  
WO/2019/010088A1
An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency m...  
WO/2018/234613A1
It is an objective to provide timing event detection. According to a first aspect, a device, comprises: a clocked conditional buffer configured to set an output of the clocked conditional buffer to a first state during a non-detection pe...  
WO/2018/236771A1
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices (T1, T2) using only low voltage transistors (inside 410) are described. The apparatus (410) and method are adapted to control multiple high...  
WO/2018/234309A1
A avalanche diode arrangement comprises an avalanche diode (11) that is coupled to a first voltage terminal (14) and to a first node (15), a latch comparator (12) with a first input (16) coupled to the first node (15), a second input (17...  
WO/2018/235373A1
The comparator with hysteresis is provided with: a comparator (110) for alternately switching between a first threshold value and a second threshold value smaller than the first threshold value in accordance with an input signal, compari...  
WO/2018/232002A1
Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signal...  
WO/2018/230338A1
The present technique relates to a clock enabler circuit capable of preventing a whisker from occurring in an output clock. A gate signal generation unit generates an input clock-enabling gate signal on the basis of an input clock and an...  
WO/2018/229610A1
A system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circ...  
WO/2018/224553A1
The invention relates to a charge controller (10) for controlling a charging process of an electric vehicle (80). In order to achieve an improved charge controller (10), in particular for improved communication of the charge controller (...  
WO/2018/226364A1
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a fi...  
WO/2018/220569A1
Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes...  
WO/2018/220470A1
Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The com...  
WO/2018/215334A1
A method for wideband generation of IQ signals involves a reference signal initially having its frequency doubled and subsequently being supplied to a master-slave D-type flip-flop (DIV2) in order to obtain an I component and a Q compone...  
WO/2018/216677A1
Provided is a comparison circuit from which a comparison result can be output without providing a half-latch circuit in a subsequent-stage logic circuit operating with the same clock as for the comparison circuit, and with which a decrea...  
WO/2018/217786A1
Methods and systems are described for obtaining, at an input stage of a sampler, a continuous-time analog differential voltage, and responsively generating an integrated analog differential voltage by discharging a pair of pre-charged ou...  
WO/2018/212937A1
Aspects of the disclosure are directed to a level shifter circuit (400). In accordance with one aspect, the level shifter circuit includes a high voltage device; a latch having a first side and a second side, wherein the latch is tied to...  
WO/2018/206708A1
The invention relates to a signal processing device for high-precision measuring of the transit time of two signals, in particular a measuring device for high-precision measuring of the transit time of at least two digital signals. The a...  
WO/2018/203149A1
A StrongARM latch comparator (500) includes first and second p-type metal- oxide-semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n- type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), where...  
WO/2018/200843A1
In methods and apparatus for detecting zero-volt crossing in a field-effect transistor, a comparator (200) compares a drain-to source voltage (Vds) of the transistor to a threshold voltage (VTH-ds). A gate voltage signal (Vgs) of the tra...  
WO/2018/194902A1
A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor s...  
WO/2018/194538A1
A zero cross detection circuit is included in a system circuit for accurately detecting a zero cross event from an alternating current power source in the system circuit. The detecting zero cross event is monitored to accurately time a c...  
WO/2018/194753A1
Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that th...  
WO/2018/188127A1
Disclosed is a storage interface. The storage interface is connected between a main controller and a storage device, and may comprise: a first programmable input/output unit, used for performing phase inversion on a clock signal output b...  

Matches 1 - 50 out of 37,936