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Matches 1 - 50 out of 37,838

Document Document Title
WO/2018/220569A1
Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes...  
WO/2018/220470A1
Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The com...  
WO/2018/215334A1
A method for wideband generation of IQ signals involves a reference signal initially having its frequency doubled and subsequently being supplied to a master-slave D-type flip-flop (DIV2) in order to obtain an I component and a Q compone...  
WO/2018/216677A1
Provided is a comparison circuit from which a comparison result can be output without providing a half-latch circuit in a subsequent-stage logic circuit operating with the same clock as for the comparison circuit, and with which a decrea...  
WO/2018/217786A1
Methods and systems are described for obtaining, at an input stage of a sampler, a continuous-time analog differential voltage, and responsively generating an integrated analog differential voltage by discharging a pair of pre-charged ou...  
WO/2018/212937A1
Aspects of the disclosure are directed to a level shifter circuit (400). In accordance with one aspect, the level shifter circuit includes a high voltage device; a latch having a first side and a second side, wherein the latch is tied to...  
WO/2018/206708A1
The invention relates to a signal processing device for high-precision measuring of the transit time of two signals, in particular a measuring device for high-precision measuring of the transit time of at least two digital signals. The a...  
WO/2018/203149A1
A StrongARM latch comparator (500) includes first and second p-type metal- oxide-semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n- type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), where...  
WO/2018/200843A1
In methods and apparatus for detecting zero-volt crossing in a field-effect transistor, a comparator (200) compares a drain-to source voltage (Vds) of the transistor to a threshold voltage (VTH-ds). A gate voltage signal (Vgs) of the tra...  
WO/2018/194902A1
A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor s...  
WO/2018/194538A1
A zero cross detection circuit is included in a system circuit for accurately detecting a zero cross event from an alternating current power source in the system circuit. The detecting zero cross event is monitored to accurately time a c...  
WO/2018/194753A1
Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that th...  
WO/2018/188127A1
Disclosed is a storage interface. The storage interface is connected between a main controller and a storage device, and may comprise: a first programmable input/output unit, used for performing phase inversion on a clock signal output b...  
WO/2018/189288A1
An asynchronous state machine (30) for a phase/frequency detector (12) operative in a phase locked loop (10) includes a short pulse suppression circuit (40, 50, 60, 70, 80) operative to suppress output pulses of duration on the order of ...  
WO/2018/179920A1
[Problem] To control delay time with high accuracy. [Solution] A delayed locked loop circuit provided with: a first delay circuit that comprises at least one first delay device and at least one second delay device, the first delay device...  
WO/2018/182585A1
A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase ...  
WO/2018/181149A1
A ring oscillator (8) comprising a plurality of logic inversion circuits (11a, 11b, 12) connected in a ring generates a multiphase clock signal. A period measurement unit (9) measures the period of a reference clock (CLK) that is input, ...  
WO/2018/180022A1
[Problem] To provide a pulse position modulation circuit capable of suppressing variations in delay time. [Solution] This pulse position modulation circuit is provided with: a delay path that comprises a plurality of delay devices connec...  
WO/2018/166130A1
Disclosed are a duty cycle adjustment apparatus and method. The apparatus comprises: a first edge extraction unit (1) for extracting a rising edge of a first clock signal; a lock determination unit (2), with an input end connected to the...  
WO/2018/164818A1
Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature ("PVT") and input common mode (Vcm) variations. This can be accomplished by separating and then varying...  
WO/2018/161083A1
In described examples, clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock (100) with active and inactive clock edges (101, 102) within a clock period (TCLOCK), and signal ca...  
WO/2018/159343A1
Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a re...  
WO/2018/160578A1
Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a powe...  
WO/2018/150184A1
A duty cycle conversion circuit portion (1) comprises N inverters (2, 4, 6, 8), wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals (10a-d) each having a duty cycle between 1...  
WO/2018/144413A1
Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direct...  
WO/2018/141878A1
A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality ...  
WO/2018/144126A1
An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by ...  
WO/2018/137751A1
A passable latch circuit (100) and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit comprises a dynamic latch comprising a first P-transistor (MPI), a first N-transistor (MNI)...  
WO/2018/136151A1
In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed vers...  
WO/2018/127721A1
A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents...  
WO/2018/127730A1
A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the...  
WO/2018/121469A1
Disclosed in the present invention are a system and a method for high-precision clock delay calibration. The calibration system comprises a NAND gate, an AND gate, a time delay chip, a multiplexer and a processing module; the multiplexer...  
WO/2018/125489A1
A proximity detector circuit that receives a single-ended sensor signal includes (a) an adaptive level control circuit maintaining the single-ended sensor signal within a predetermined voltage range relative a common mode reference signa...  
WO/2018/120555A1
The present invention discloses a phase interpolator circuit and a method for improving the linearity thereof, the phase interpolator circuit comprising: N phase interpolator units, N≥2; a phase interpolator unit comprises a differenti...  
WO/2018/118274A1
A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference sign...  
WO/2018/116109A1
Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW ...  
WO/2018/119081A1
An output clock frequency (102, 202, 850) of an adaptive oscillator circuit (120, 200, 800, 1000) changes in response to noise on an integrated circuit power supply line (220, 820). The circuit features two identical delay lines (210, 81...  
WO/2018/112302A1
A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to...  
WO/2018/107034A1
A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the comm...  
WO/2018/096973A1
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...  
WO/2018/090650A1
The invention discloses a clock compensation circuit, a clock circuit, and a microcontroller. The clock compensation circuit comprises: a detection circuit used to detect a capacitance control parameter capable of affecting a clock frequ...  
WO/2018/087914A1
The present invention is configured so as to comprise: a high-pass filter (2) that eliminates an offset included in an AC signal Vin input from a signal input terminal (1); and a waveform restoration unit (3) that, using a time constant ...  
WO/2018/087187A1
The invention relates to a method for transferring target values (S) by means of target value signals and parameterization values (P) by means of parameterization signals for parameterizing an electric motor, in particular an EC motor vi...  
WO/2018/089121A2
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/081883A1
Method and implementation of a detector of rapid pulses in the power supply voltage of integrated circuits, which involves conditioning the rapid pulse applied to the power supply voltage to trigger the security alarm, more specifically ...  
WO/2018/083893A1
The present invention improves the detection accuracy of a timing error in a semiconductor integrated circuit provided with a storage element that operates in synchronization with a clock signal. A delay unit delays a data signal by two ...  
WO/2018/074251A1
The present technology relates to a signal processing device, a signal processing method, and a program which enable the reduction of the effect of crosstalk. Provided are a plurality of comparators, a delay unit which delays outputs fro...  
WO/2018/073562A1
An apparatus for synchronizing an input signal (D) that is asynchronous to a clock signal (CLK) received by the apparatus. The apparatus comprising selection circuitry (104) configured to select the input signal and to generate a pair of...  
WO/2018/068330A1
Provided are a rectification circuit and a rectifier, relating to the field of electronic technologies and capable of operating normally when a voltage of an AC signal input to the rectification circuit is less than Vth. The rectificatio...  
WO/2018/071153A2
Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit gener...  

Matches 1 - 50 out of 37,838