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Matches 1 - 50 out of 37,587

Document Document Title
WO/2018/012083A1
The present invention reduces a leak current while reducing low-frequency noise in an AGC circuit provided with a transistor that shifts to an on state or an off state according to the level of a signal. A switching circuit is provided w...  
WO/2018/010156A1
An electronic chip signal modulation method and system, the method comprising the following steps: obtaining signal information of an electronic chip (101); processing the signal information to obtain a peak value of the signal informati...  
WO/2018/008140A1
A pulse-width correction circuit (1) comprising: a fixing unit (10) that fixes an output signal S_OUT at a high level if, after a state in which the output signal S_OUT is low-level has continued for a first period of time, an input sign...  
WO/2018/001701A1
A driving circuit (10)to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10).In a first operating state/pre-ch...  
WO/2018/000330A1
A method and system for preprocessing a signal of an electronic chip. The method comprises the following steps: sampling signal data of an electronic chip (101); analyzing and processing the sampled data to acquire the rate of change of ...  
WO/2018/000839A1
A new on-line monitoring unit for an ultra-wide voltage and a control circuit therefor. Compared with an ordinary on-line monitoring unit, it is not necessary to reserve a delay unit to replace an original trigger in the ordinary on-line...  
WO/2017/222620A1
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...  
WO/2017/217139A1
Provided is a chattering removal circuit with which it is possible to improve the response of an output signal to variations in an input signal, at low cost and using a simple configuration. A chattering removal circuit (30) removes chat...  
WO/2017/219039A1
In described examples of a communication system (10), the system (10) includes a data transmitter (12) configured to generate a digital communication signal and a data receiver (14) configured to receive the digital communication signal....  
WO/2017/212699A1
The purpose of the present invention is to provide a sensor array device which accurately and rapidly determines and outputs data detected by a sensor. A sensor array device is provided with a sensor, and a comparison unit which compares...  
WO/2017/203624A1
The purpose of the present invention is to achieve size reduction and simplification of the circuit configuration of an intelligent power module (IPM) through phase synchronization of the IPM. The IPM pertaining to the present invention ...  
WO/2017/199790A1
In a monitor circuit (10), a data signal (D1) is propagated from an FF (11) to an FF (12) via a data delay circuit (16). The data delay circuit (16) selects, in accordance with a selection signal (TN1), any one from among data paths (161...  
WO/2017/197946A1
Disclosed is a PVTM-based, wide-voltage-range clock stretching circuit. The circuit comprises a PVTM circuit module, a phase clock generation module, a clock synchronization selection module, and a control module. The PVTM circuit module...  
WO/2017/195615A1
The present technology relates to a detection device and a detection method that enable a lock state to be determined more accurately. A first edge detector detects whether an edge of a second clock signal is present in one cycle of a fi...  
WO/2017/190948A1
The invention relates to an integrated semiconductor circuit (10) comprising at least one input terminal (12; 12_1 to 12_E'). A debouncing device (14) that is integrated into the semiconductor circuit in order to debounce an input signal...  
WO/2017/189739A1
A system and method for optical tomography including illuminating an object with pulsing stimulus light and pulsing the stimulus light at a repetition frequency having a pulse period that is greater than a dead-time of a detector. Coordi...  
WO/2017/189494A1
A circuit (100) for providing back-up power includes a switching circuit (118, 112) configured to be coupled to a first power source (102) and a second power source (104). The circuit includes a domain voltage level monitor circuit (106)...  
WO/2017/184386A1
A clock generator (500) includes: a first input (502) to receive a global clock signal (216); a second input (504) to receive a completion signal (516); and a third input (506) to receive differential outputs (116, 312, 314) in a convers...  
WO/2017/177103A1
Aspects of the invention provide improvements to electromagnetic and other wave-based ranging systems, e.g., RADAR or LIDAR systems, of the type having transmit logic that transmits a pulse based on an applied analog signal. The improvem...  
WO/2017/165107A1
Methods, systems, and devices for wireless communication are described. An internal state of a frequency divider of a local oscillator (LO) may be stored using a storage device in order to facilitate phase flipping of one or more signals...  
WO/2017/156360A1
An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate...  
WO/2017/156241A1
An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.  
WO/2017/151260A1
A pulse generator discharge circuit is disclosed. The circuit includes one or more discharge stages, each discharge stage including a plurality of control input terminals. The circuit also includes first and second discharge terminals, a...  
WO/2017/149956A1
This signal output circuit (1, 51) comprises a slope control circuit (6), a capacitor (9), a noise detection circuit (14, 31, 41) and a malfunction prevention circuit (7). The slope control circuit charges and discharges the capacitor, t...  
WO/2017/145392A1
The purpose of the present invention is to provide an electrical apparatus allowing a drastic reduction in the number of contact input terminals. An electric apparatus 3 is equipped with an input device 1 that receives an analog signal. ...  
WO/2017/144235A1
The invention relates to a communication interface between a control unit and an electric load unit, particularly a load unit having a pump motor in a motor vehicle, wherein the control unit is designed as a transmitter and/or receiver, ...  
WO/2017/143315A1
An embodiment in accordance with the present invention provides a system and method of physically modulating a digital signal across a medium. A signal is sent one bit at a time (serially) as a period of high voltage followed by a period...  
WO/2017/142696A1
The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The firs...  
WO/2017/136052A2
A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated...  
WO/2017/136052A3
A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated...  
WO/2017/131844A1
A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs (121) coupled to receive a plurality of clock signals; a plurality of transistor pa...  
WO/2017/131934A1
The present disclosure is directed to methods and systems for providing information about a target based on pulse widths. The information can be provided in a formatted output signal which uses a pulse width protocol to code information ...  
WO/2017/123269A1
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devic...  
WO/2017/119488A1
A serializer device 1 is provided with a first latch unit 11, a second latch unit 12, a conversion unit 13, a frequency division unit 14, a load signal generation unit 15, a phase difference detection unit 16, and a reset indication unit...  
WO/2017/118872A3
Techniques and devices for differential signal repeating are described. A differential signal repeating method may include receiving an input differential signal pair including first and second input signals received at first and second ...  
WO/2017/119220A1
In order to simplify a comparison device of an analog-to-digital conversion apparatus, in the comparison device, an input signal is input to control terminals of a plurality of signal input transistors. A reference input transistor forms...  
WO/2017/112222A1
An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.  
WO/2017/108264A1
The invention relates to a method and an apparatus (1) with a circuit arrangement (3) comprising at least one mechanical switch (5) which is used to open and/or close an electrical contact (7), and a processor unit (9) which is used to c...  
WO/2017/101167A1
A controllable splitting method for a large current pulse and an apparatus therefor. The method comprises: electrically connecting a silicon carbide photo-conductive switch between input and output ends of a current pulse; connecting a t...  
WO/2017/100666A1
A wireless communication method includes generating a pilot signal that is represented using a complex exponential signal having a first linear phase in a time dimension and a second linear phase in a frequency dimension; and transmittin...  
WO/2017/098624A1
A semiconductor device driving circuit is provided with: a signal transmission circuit including a first level shift circuit for level-shifting an input signal having a first voltage level and generating, on the basis of the input signal...  
WO/2017/096766A1
A method and device for eliminating interference and a smart television set. The method comprises: determining whether an interference pulse exists in a current inter-integrated circuit (IIC) bus when sensing a read/write data instructio...  
WO/2017/094310A1
The present invention improves the operating range of a phase detector equipped with flip-flops and improves the jitter resistance of a reception circuit. This phase detector is provided with a retention unit and a detection unit. In the...  
WO/2017/095601A1
Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to t...  
WO/2017/080925A1
In a data processing architecture comprising a control unit and converters CNj to be synchronised on an active edge of a common reference clock CLK, a synchronisation method involves the arrangement of the converters into at least one se...  
WO/2017/075296A1
A dual stage power converter capable of being installing in a one-gang box and powering an LED load is presented. The dual stage converter can include a power factor correction (PFC) stage operating in transition mode and a resonant conv...  
WO/2017/068035A1
Signal processing method for histogram generation, and corresponding device and use. A signal processing method for histogram generation from a plurality of event detectors, that generate event signals as a response to external events, a...  
WO/2017/064076A1
Disclosed is a method for controlling a semiconductor switch (HS) using a pulse-width-modulated control signal (PWM). A check is made (S100) to determine whether a current duty cycle (Tm) of the control signal (PWM) lies within a duty cy...  
WO/2017/051654A1
A ringing suppression circuit that is connected to a transmission line for transmitting a differential signal changing between binary levels of High and Low by means of a pair of high and low potential side signal lines and that suppress...  
WO/2017/049989A1
A high speed low power consumption dynamic comparer, comprising a latch, an AND gate, a delay unit, and an XNOR gate. The latch has first to third control terminals. Outputs of the latch pass through inverters I1 and I2 respectively to p...  

Matches 1 - 50 out of 37,587