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Matches 1 - 50 out of 37,774

Document Document Title
WO/2018/166130A1
Disclosed are a duty cycle adjustment apparatus and method. The apparatus comprises: a first edge extraction unit (1) for extracting a rising edge of a first clock signal; a lock determination unit (2), with an input end connected to the...  
WO/2018/164818A1
Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature ("PVT") and input common mode (Vcm) variations. This can be accomplished by separating and then varying...  
WO/2018/161083A1
In described examples, clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock (100) with active and inactive clock edges (101, 102) within a clock period (TCLOCK), and signal ca...  
WO/2018/159343A1
Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a re...  
WO/2018/160578A1
Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a powe...  
WO/2018/150184A1
A duty cycle conversion circuit portion (1) comprises N inverters (2, 4, 6, 8), wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals (10a-d) each having a duty cycle between 1...  
WO/2018/144413A1
Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direct...  
WO/2018/141878A1
A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality ...  
WO/2018/144126A1
An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by ...  
WO/2018/137751A1
A passable latch circuit (100) and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit comprises a dynamic latch comprising a first P-transistor (MPI), a first N-transistor (MNI)...  
WO/2018/136151A1
In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed vers...  
WO/2018/127721A1
A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents...  
WO/2018/127730A1
A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the...  
WO/2018/121469A1
Disclosed in the present invention are a system and a method for high-precision clock delay calibration. The calibration system comprises a NAND gate, an AND gate, a time delay chip, a multiplexer and a processing module; the multiplexer...  
WO/2018/125489A1
A proximity detector circuit that receives a single-ended sensor signal includes (a) an adaptive level control circuit maintaining the single-ended sensor signal within a predetermined voltage range relative a common mode reference signa...  
WO/2018/120555A1
The present invention discloses a phase interpolator circuit and a method for improving the linearity thereof, the phase interpolator circuit comprising: N phase interpolator units, N≥2; a phase interpolator unit comprises a differenti...  
WO/2018/118274A1
A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference sign...  
WO/2018/116109A1
Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW ...  
WO/2018/119081A1
An output clock frequency (102, 202, 850) of an adaptive oscillator circuit (120, 200, 800, 1000) changes in response to noise on an integrated circuit power supply line (220, 820). The circuit features two identical delay lines (210, 81...  
WO/2018/112302A1
A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to...  
WO/2018/107034A1
A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the comm...  
WO/2018/096973A1
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...  
WO/2018/090650A1
The invention discloses a clock compensation circuit, a clock circuit, and a microcontroller. The clock compensation circuit comprises: a detection circuit used to detect a capacitance control parameter capable of affecting a clock frequ...  
WO/2018/087914A1
The present invention is configured so as to comprise: a high-pass filter (2) that eliminates an offset included in an AC signal Vin input from a signal input terminal (1); and a waveform restoration unit (3) that, using a time constant ...  
WO/2018/087187A1
The invention relates to a method for transferring target values (S) by means of target value signals and parameterization values (P) by means of parameterization signals for parameterizing an electric motor, in particular an EC motor vi...  
WO/2018/089121A2
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/081883A1
Method and implementation of a detector of rapid pulses in the power supply voltage of integrated circuits, which involves conditioning the rapid pulse applied to the power supply voltage to trigger the security alarm, more specifically ...  
WO/2018/083893A1
The present invention improves the detection accuracy of a timing error in a semiconductor integrated circuit provided with a storage element that operates in synchronization with a clock signal. A delay unit delays a data signal by two ...  
WO/2018/074251A1
The present technology relates to a signal processing device, a signal processing method, and a program which enable the reduction of the effect of crosstalk. Provided are a plurality of comparators, a delay unit which delays outputs fro...  
WO/2018/073562A1
An apparatus for synchronizing an input signal (D) that is asynchronous to a clock signal (CLK) received by the apparatus. The apparatus comprising selection circuitry (104) configured to select the input signal and to generate a pair of...  
WO/2018/068330A1
Provided are a rectification circuit and a rectifier, relating to the field of electronic technologies and capable of operating normally when a voltage of an AC signal input to the rectification circuit is less than Vth. The rectificatio...  
WO/2018/071153A2
Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit gener...  
WO/2018/071167A1
Some embodiments include a high voltage nonlinear transmission line that includes a high voltage input configured to receive electrical pulses having a first peak voltage that is greater than 5 kV having a first rise time; a plurality of...  
WO/2018/071114A1
Digital-to-analog converter (master DAC) circuitry is disclosed that is programmable to set a controlled slew rate for pulses that are otherwise defined as having sharp amplitude transitions. For example, when producing a biphasic pulse,...  
WO/2018/071153A3
Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit gener...  
WO/2018/068847A1
The present invention relates to an apparatus and method for generating an analog output voltage perfectly linear according to the digital input code associated with a capacitor array DAC. An array of n capacitors is split into a first a...  
WO/2018/069046A1
The invention relates to a method for recognizing a bouncing motion of a pedal (24), comprising recognizing a restoration of the pedal (24) into an idle position (18) and detecting the occurrence of the bouncing motion of the pedal (24) ...  
WO/2018/058915A1
Disclosed is a clock signal loss detection device, comprising: a first delay unit, a second delay unit, a D flip-flop, a first NOT gate, a second NOT gate, and an AND gate. An input end of the first delay unit, a clock end of the D flip-...  
WO/2018/055149A1
The invention relates to a device (210) which includes: an analysis module (220) generating a binary signal (d(t)) for pulse detection in an incident pulse signal (s(t)); a multiplier (221) weighting the incident pulse signal (s(t)) by t...  
WO/2018/054038A1
A protection circuit of a bidirectional converter (13) and a power consumption system having a power-storage function. The protection circuit is applied to a power consumption system having a power-storage function, and comprises: a sing...  
WO/2018/057350A1
Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals ...  
WO/2018/051388A1
[Problem] To provide an analog circuit for use in a position indicator, which is of low power consumption and of high noise-resistance. [Solution] An analog circuit 90 according to the present invention is connected to an electrode 21 th...  
WO/2018/052982A2
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may...  
WO/2018/050798A1
The invention relates to a signal processing device for the highly precise measurement of the delay time of two signals. The aim of the invention is to provide a signal processing device and a measuring device for the highly precise meas...  
WO/2018/052982A3
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may...  
WO/2018/048912A1
Current generation circuitry for an Implantable Pulse Generator (IPG) is disclosed. The IPG comprises a plurality of PDACs and NDACs for souring currents to electrode nodes. The PDACs and NDACs can be configured as pairs to each provide ...  
WO/2018/045770A1
A control circuit (100, 400, 903), a control method, and an electronic device (900). The control circuit (100, 400, 903) comprises: a first control sub-circuit (101,401), which is configured to receive a first power signal (VDD1) from a ...  
WO/2018/044725A1
A transition glitch suppression circuit (400) can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal (402). The transition glitch suppression circuit has a delay element (404)...  
WO/2018/044665A1
One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic oper...  
WO/2018/038921A1
Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is prov...  

Matches 1 - 50 out of 37,774