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Matches 1 - 50 out of 38,413

Document Document Title
WO/2020/261039A1
Provided is a semiconductor device withi minimized increase in circuit area and less power consumption. The semiconductor device has a high-frequency amplification circuit, an envelope detection circuit, and power supply circuit. The pow...  
WO/2020/262771A1
The present invention is formed so that a plurality of delay cells provide square-wave voltages to a plurality of transistors in accordance with specific time periods, the plurality of transistors transfer current to an oscillator in acc...  
WO/2020/257855A1
An evacuation device comprising a microphone to record an audible signal, for conversion to a visual signal, in the form of a flashing light to aide evacuation from a smoke filled environment. In the preferred embodiment, the unit senses...  
WO/2020/263378A1
Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a sourc...  
WO/2020/255854A1
A signal detection circuit for detecting a signal subject to detection, which is a signal from a main terminal of a switching element (2), by means of a comparison with a reference signal, the signal detection circuit being provided with...  
WO/2020/255853A1
This signal detection circuit is provided with: a first capacitor (C1), one terminal of which is connected to one main terminal of a switching element (2); a second capacitor (C2), one terminal of which is connected to the other main ter...  
WO/2020/255371A1
A variable delay circuit according to the invention comprises: a first delay circuit including a plurality of first delay elements that can be switched between returning a received signal to the input side and forwarding the received sig...  
WO/2020/255722A1
The present invention suppresses influence against the miniaturization and high density integration of a chip and adds an inductor. An avalanche photo diode sensor pertaining to an embodiment is provided with: a first chip including an a...  
WO/2020/248318A1
A bidirectional adaptive clock circuit supporting a wide frequency range, belonging to the technical field of basic electronic circuits. Said circuit consists of a phase clock generation module, a phase clock selection module, an adaptiv...  
WO/2020/246092A1
Provided is a phase synchronization circuit constituted by a digital circuit, wherein a circuit for generating phase difference information is reduced in terms of circuit scale. A multiphase clock generation circuit generates a plurali...  
WO/2020/247005A1
Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a passgate, a passgate inverter, a leakage compensation unit, and an inverter. The passgate may be coupled between a flip-flop data input termin...  
WO/2020/237648A1
The present application relates to the field of display, and provides a signal frequency adjustment method and apparatus, a display apparatus, and a storage medium. The method comprises: obtaining a first number of times that a reference...  
WO/2020/235090A1
There are indicated, on the basis of a peek point of an integrated waveform of a received signal (b) per one-bit time, a timing to reset an integrated value of the received signal (b) per one-bit time and a timing to determine whether th...  
WO/2020/236209A1
A pulse signal compensation circuit of a pulse generator can include a pulse measurement circuit and a compensation generator circuit. The pulse measurement circuit can be configured to receive a plurality of pulse signals and to generat...  
WO/2020/229265A1
The invention relates to a method (700) for determining a time of a flank (200) in a signal (132), wherein the method (700) comprises a step of reading (710) the signal (132) and has a master clock (210) for operating a digital evaluatio...  
WO/2020/224289A1
Provided are an enhanced substrate-based comparator and an electronic device, said comparator comprising: a cross-coupled latch (1), used for connecting an input signal to a gate of a cross-coupled MOS transistor to form a first input te...  
WO/2020/225721A1
A clock recovery circuit (104) includes a first pulse circuit (106), a second pulse circuit (108), a state change circuit (110) connected to the first pulse circuit and the second pulse circuit and a first delay circuit (112) connected t...  
WO/2020/218472A1
Provided are a hysteresis comparator with which it is possible to obtain desired characteristics even when an IC chip comprising a comparator with no hysteresis or a comparator with a small hysteresis width is used, and a communication c...  
WO/2020/214377A1
Apparatus and associated methods relating to a switch leakage compensation delay circuit (405a) include a compensating transistor (To) configured to passively bypass a leakage current around a capacitor (Co) that connects in series with ...  
WO/2020/210272A1
In described examples, an amplifier (100) can be arranged to generate a first stage (110) output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source II thr...  
WO/2020/210359A1
Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the...  
WO/2020/210145A1
A circuit includes a peak detector (220), a diode (DO), a dynamic clamp circuit (210), and an offset correction circuit (250). The peak detector (220) generates a voltage on the peak detector output proportional to a lowest voltage on th...  
WO/2020/208927A1
The purpose of the present invention is to reduce errors that are caused by changes in delay time when driving a light-emitting element. A light emission driving device (10) comprises: a light emission current detection unit (401)(12); a...  
WO/2020/193579A1
The invention relates to a setting device (1) for setting an effective value of an electric load current at a time-variant load (2). There is provision for the setting device (1) to be configured to provide a voltage pulse sequence (4), ...  
WO/2020/190958A1
A control module may modify a duty cycle and phase timing for each phase of a multiphase cycle, based the center of a synchronization signal, to cause an equivalent transition time between each phase of the multiphase cycle.  
WO/2020/191290A1
A differential-slope-limiting-switch and method are provided. Generally, the switch includes a first transistor having a first source-drain (SD) and well coupled to a first port of the switch, a gate, and a second SD, and a second transi...  
WO/2020/190825A1
A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as ...  
WO/2020/186471A1
A delay circuit and a drive device, wherein the delay circuit may comprise at least two branches, the at least two branches are connected in parallel, and each of the at least two branches has a different delay; and the delay circuit com...  
WO/2020/185341A1
One embodiment includes a clock distribution resonator system (10). The system includes a clock source (12) configured to generate a clock signal (CLK) having a predefined wavelength, and a main transmission line (16) coupled to the cloc...  
WO/2020/183808A1
A solid-state image capturing element is provided with a comparator which compares a reference signal with a pixel signal, wherein the image quality of image data is enhanced. According to the present invention, a voltage dividing circ...  
WO/2020/180403A1
An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to gen...  
WO/2020/179023A1
This time-to-digital converter (100, 100a, 100b) is configured such that a first flip-flop group (121) has first to N-th (N is a natural number not less than 2) D-type flip-flop circuits (121-1, 121-2, 121-3, ..., 121-N), wherein: D term...  
WO/2020/174303A1
The present invention provides a novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electrical apparatus, and the l...  
WO/2020/173733A1
A system for transmitting a value by means of a pulse-width-modulated signal is shown. The system comprises a transmitter and a receiver. The transmitter is configured to capture the value and to output a pulse-width-modulated signal, th...  
WO/2020/169941A1
The invention relates to devices and methods of characterising a single unknown pulse signal. They create multiple replica of the original that may be more reliably measured, by dividing the signal through nodes and using different signa...  
WO/2020/166645A1
A DTC 102, in response to an input reference clock REF, generates a first reference clock REFA. A delay circuit 122 delays the first reference clock REFA and generates a second reference clock REFB. A TDC 104 converts a phase difference ...  
WO/2020/155086A1
Disclosed are a signal processing circuit, for use in performing signal processing with respect to a transducer output signal, where the transducer output signal is generated by a transducer being triggered by a transducer input signal a...  
WO/2020/159746A1
A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f«,.a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VC...  
WO/2020/157118A1
The present invention relates to switched mode power supplies, and more particularly relates to an isolated DC-DC power converter comprising a secondary side active synchronous rectification circuit. The active synchronous rectification ...  
WO/2020/154989A1
A method for adjusting duty cycle, a controller chip (101), and a flash memory (1000); the controller chip (101) currently sends a signal to a storage array (11), the signal being sent from the controller chip (101) after passing through...  
WO/2020/086760A3
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is config...  
WO/2020/147094A1
Disclosed is a signal generating circuit (100), which is used for generating an emission signal to trigger a first transducer to generate a first transducer output signal. The signal generating circuit comprises: a signal generating unit...  
WO/2020/150132A1
A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit (700). The ADC is configured to generate a series of digital codes. The hysteresis circuit (700) is configured to: (a) determine that a first digital code o...  
WO/2020/140469A1
A comparator (100). The comparator (100) comprises: a first current source circuit (110), a preamplifier circuit (120), an amplifier circuit (130), a comparison circuit (140), and an output circuit (150). The first current source circuit...  
WO/2020/135955A1
An example system includes an input terminal operable to receive an input signal having first pulses, a first delay circuit, a second delay circuit, and a latch circuit. The first delay circuit is operable to generate a first delay signa...  
WO/2020/139371A1
Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (...  
WO/2020/139451A1
Various embodiments relate to classifying comparators (100) based on comparator offsets. A method may include applying, via a strobe (M5 gate), a first voltage to each of a first input (Inp) and a second input (Inn) of a comparator to ge...  
WO/2020/130338A1
Provided is a delayer in which an RF TTD and an analog TTD are connected through a mixer in a multistage manner, in order to configure a delay circuit having high resolution, long delay time, and a small gain change. A delayer according ...  
WO/2020/131272A1
In certain aspects, a comparator (100) includes a first inverter (110) having an input, an output, and a voltage supply input (112), wherein the input of the first inverter and the output of the first inverter are coupled together, and t...  
WO/2020/128722A1
Provided is a hysteresis comparator having a small circuit area and exhibiting a low power consumption. The hysteresis comparator comprises a comparator, a switch, a first capacitor, a second capacitor and a logic circuit, wherein a firs...  

Matches 1 - 50 out of 38,413