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Matches 1 - 50 out of 38,215

Document Document Title
WO/2020/100673A1
The present technology relates to a signal processing device and a signal processing method which enable a duty ratio of a pulse to be easily adjusted. A phase comparison unit outputs a phase difference signal corresponding to a phase di...  
WO/2020/100374A1
This delay time detection circuit comprises a clock generation unit (11), counting unit (12), subscale signal generation unit (13), and delay time calculation unit (14). The clock generation unit (11) generates a subscale clock signal on...  
WO/2020/098349A1
A clock cycle-based pulse width modulation signal duty cycle multiplication circuit, comprising: a duty cycle multiplication enabling pulse generating circuit (101), an input end thereof inputting a clock signal (CLK) and an original pul...  
WO/2020/097019A1
A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit comprises a pickup coil and a threshold...  
WO/2020/086121A1
An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level ...  
WO/2020/076378A1
An operational amplifier with totem pole connected output transistors having inputs coupled to multiplexers for selectable coupling of signals and voltage levels thereto. The high and low output transistors may be forced hard on or hard ...  
WO/2020/076159A1
An Circuit (21) arranged for providing a delayed output signal (OUT) from an input signal (IN), wherein the circuit comprises n (4) branches in a sequence of branch 1 to n (4),each having an input and an output, wherein each branch (Bran...  
WO/2020/068089A1
A zero-crossing detection method, and devices incorporating the method, enable a selectively enabled bias to pull-up a zero-crossing signal, thereby enabling monitoring of the zero-crossing of both half-cycles of the alternating current ...  
WO/2020/065816A1
A comparison circuit for outputting the result of a high/low comparison of a reference signal and a comparison signal is provided with: two hysteresis comparators 2A and 2B; input circuits 1A and 1B that each input a reference signal and...  
WO/2020/066327A1
An objective of the present technique is to provide an image sensor and a photodetector that are capable of reducing power consumption of an A/D conversion unit. An image sensor is provided with a comparator comprising: a differential in...  
WO/2020/068206A1
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of tw...  
WO/2020/057269A1
A high-speed regenerative comparator circuit, comprising: a signal input stage connected to an input end for differential signal input; a latch for caching and serving as a differential signal output end; a current source connected to th...  
WO/2020/052929A1
The invention relates to a device (1; 1a-1d) for generating a wake-up signal for an electronic device (4) during a plugging process of a charging cable, wherein the device (1; 1a-1d) is designed to generate the wake-up signal when there ...  
WO/2020/054629A1
A solid-state imaging element (10) is provided with: a noise cancelation signal generating circuit (12) that is connected to a pixel power source (PW), and that performs gain switching and polarity inversion on a generated first noise ca...  
WO/2020/050319A1
A switching drive circuit (100) comprises at least a hysteresis delay circuit that performs a hysteresis delay process with respect to a control signal. The hysteresis delay circuit includes a charge/discharge circuit (101), a comparator...  
WO/2020/049039A1
A circuit assembly (100') and a method for operating an LED module (10, 10') is provided, the LED module comprising a plurality of module units (14) which are each interconnected between common connection lines (16, 17) in a sequential o...  
WO/2020/047672A1
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more ph...  
WO/2020/044664A1
The purpose of the present invention is to stably adjust a duty cycle of a clock signal in the event of a drop in source voltage. The duty cycle correction circuit is equipped with an inverting buffer, a capacitor, a low-pass filter, an ...  
WO/2020/046840A1
A differential phase and amplitude detector circuit is presented. Two source follower circuits respectively based on NMOS and PMOS transistors are used to charge and discharge a sampling capacitor asymmetrically to provide a measurement ...  
WO/2020/039977A1
A semiconductor circuit device according to the present disclosure comprises: a control circuit that controls a clock signal input from the outside; a drive circuit that performs a switching operation according to a pulse signal provided...  
WO/2020/041113A1
Aspects of the description provide a method (200). In some examples, the method includes detecting a transition in an input signal (IN) (205), generating a bias current based on the detected transition in IN (210), and modifying a charge...  
WO/2020/033816A1
An example power multiplexer (100) includes: a first transistor (105) coupled to a first input (102); a second transistor (106) coupled to the first transistor (105) to couple a first voltage at the first input (102) to an output (101); ...  
WO/2019/074727A8
An example digital-to-time converter (DTC) (102) includes: a delay chain circuit (301) having a plurality of delay cells (302) coupled in sequence, the delay chain circuit including a first input (Fref) to receive a first clock signal an...  
WO/2020/031330A1
This semiconductor integrated circuit is provided with: a phase synchronization circuit that is synchronized to a reference clock signal and that generates a synchronous clock signal in which the reference clock signal is multiplied; an ...  
WO/2020/032915A1
Networks, methods, and circuitries are provided that propagate an actuator signal to a plurality of devices in a respective plurality of voltage domains (VD1-VD4). An exemplary network (310) includes a first signal path between an actuat...  
WO/2020/025941A1
This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal(SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Al...  
WO/2020/024149A1
Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node res...  
WO/2020/023974A1
Some embodiments include a high voltage pulsing power supply. A high voltage pulsing power supply may include: a high voltage pulser having an output that provides pulses with an amplitude greater than about 1 kV, a pulse width greater t...  
WO/2020/022388A1
[Problem] To achieve a configuration that does not include a diode susceptible to temperature. [Solution] The present invention is provided with: a capacitor 42c wherein one end section thereof has a difference signal Vd0 input thereto a...  
WO/2020/021392A1
An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting comm...  
WO/2020/023965A1
A high voltage power system is disclosed. In some embodiments, the high voltage power system includes a high voltage pulsing power supply; a transformer electrically coupled with the high voltage pulsing power supply; an output electrica...  
WO/2020/022387A1
[Problem] To generate a code identifying signal that can identify a code corresponding to a logic signal transmitted to a communication channel without being connected to the communication channel via a connector. [Solution] The present ...  
WO/2020/013916A1
A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage suppl...  
WO/2020/012943A1
The present technology relates to a comparator and an imaging device which make it possible to easily change an operation point potential of the comparator. A pixel signal output from a pixel and a reference signal the voltage of which c...  
WO/2020/013226A1
A signal processing circuit (13) having: a plurality of first circuits (41-1) each having a first interval signal output circuit (51) for outputting a first interval signal representing a time interval between a first timing at which a f...  
WO/2020/014444A1
A millimeter wave (MMW) circuitry includes a phase modulation circuitry, a plurality of amplifier multiplier chain circuitries and a power combiner circuitry. The phase modulation circuitry is configured to receive input data and a plura...  
WO/2020/013101A1
A signal processing circuit (12) outputs a first output signal at a first timing, at which a first input signal changes, and outputs a second output signal at a second timing, at which a second input signal changes, when the first timing...  
WO/2019/234412A3
The present invention relates to a handheld device (10) for detecting a partial discharge event, the device comprising: • a first probe (12) having a first partial discharge sensor (14) disposed within; and • a second probe (20) havi...  
WO/2020/005438A1
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communi...  
WO/2020/003980A1
Provided is a solid-state imaging device with which it is possible to improve the dynamic range of an ADC and thereby improve imaging characteristics. Provided is a solid-state imaging element (11) comprising a pixel array (12) having a ...  
WO/2019/237366A1
Disclosed in the present invention is a reference clock duty ratio calibration circuit, comprising a low-noise low-dropout regulator, an oscillation circuit, a duty ratio adjustment circuit and a duty ratio calibration circuit. The duty ...  
WO/2019/238144A1
Disclosed are a data signal detection apparatus, and a mobile industry processor interface radio frequency front-end slave device and system, the apparatus comprising: a first acquisition circuit, a second acquisition circuit and an outp...  
WO/2019/239984A1
This semiconductor device comprises: first through N-th PLL circuits which operate in synchronization with a common reference clock signal and which respectively output first through N-th clock signals; a majority circuit that carries ou...  
WO/2019/237114A1
Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits havin...  
WO/2019/234412A2
The present invention relates to a handheld device for detecting a partial discharge event, the device comprising: a first probe having a first partial discharge sensor disposed within; and a second probe having a second partial discharg...  
WO/2019/234037A1
The invention relates to a comparator circuit (1), which has an input stage for a first voltage and for a second voltage and which is designed for comparing the first voltage and the second voltage, and which is designed to generate a di...  
WO/2019/234484A1
A system and method for generating a waveform having a burst modulated ultrasound sweep carrier wave with encapsulated sonic artefacts is disclosed. The system includes a transducer; and a microcontroller operatively connected to the tra...  
WO/2019/231338A1
Disclosed is a method for modelling a distorted energy spectrum in a multi-energy x-ray CT imaging system using probability distribution functions, the method including taking open beam measurements across a range of fluxes, estimating t...  
WO/2019/231489A1
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty- cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smalle...  
WO/2019/231574A1
A system is disclosed. The system includes a first stage (M12, M14) configured to receive an input voltage (VIN) and a reference voltage (VREF), the first stage including an input transistor pair (M12, M14), wherein the input voltage is ...  

Matches 1 - 50 out of 38,215