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JP4026879B2 |
The circuit has a capacitor (20) which is charged at constant current to integrate of the height of each edge during a time period at maximum equal to half the period corresponding to the maximum frequency. The circuit has two symmetrica...
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JP3990323B2 |
An approach for reliably communicating over a satellite (111) in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured ...
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JP3966852B2 |
To provide a serial communication apparatus which is capable of detecting data on the basis of a decision by majority to perform communication immune to noise and further, suppressing as little as possible a timing deviation caused by mi...
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JP3860795B2 |
The invention provides a circuit configuration for demodulating a voltage that is ASK modulated by altering the amplitude between a low level and a high level. In this case, a first and a second charging circuit each produce a charging v...
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JP3851906B2 |
To provide a pulse generating circuit capable of generating an output pulse signal having a large pulse width. The pulse generating circuit includes a first logic means 42, a second logic means 44, a first delay means 72, and a second de...
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JP3822632B2 |
[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problems] The present invention provides a digital data transfer method for al...
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JP2006507725A |
Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.
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JP3737390B2 |
To provide a receiver for a wireless telecommunication system, by which signal processing in a comparatively wide zone of a received signal is conducted without increasing the distortion of a signal and a large number of the received sig...
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JP3734175B2 |
To provide a delay apparatus with high resolution without increasing the circuit scale. The delay apparatus (delay circuit 10) for inputting a signal with periodicity and outputting the signal with a delay by a prescribed time T0 is prov...
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JP2005198240A |
To provide a semiconductor circuit, capable of effectively applying a filter function to both the "L-level" noise superimposed during originally "H" signal periods and "H-level" noise superimposed during originally "L" signal periods.An ...
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JP3674166B2 |
To properly control a selection reception state of an AM broadcast wave signal by using a demodulation output signal obtained by applying an AM intermediate frequency signal to an FM demodulation section for controlling a selection recep...
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JP2005507319A |
A method for selectively assembling a molecular device on a substrate comprises contacting the first substrate with a solution containing molecular devices; impeding bonding of the molecular devices to the substrate such that application...
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JP2005057770A |
To provide a method and a device to reduce the number of pins used for volume control signal and to control an audio output volume.The invention relates to a method and a device 50 to generate and control a volume of a speaker 14 in an i...
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JP3567747B2 |
Disclosed are an integration circuit capable of substantially raising the ratio of a current to a capacitance, I/C, and voltage-controlled oscillator and frequency-voltage converter which employ the integration circuit. The integration c...
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JP3553753B2 |
To enable a PLL circuit to reduce a frequency of an operation clock that detects a pulse. A pulse detecting part 10 samples a pulse signal to be demodulated, based on an operation clock. An operation clock generating part 9 generates an ...
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JP2004135306A |
To provide a comparator having hysteresis wherein high speed switching is enabled, without being accompanied by a large current consumption.This comparator is provided with a first transistor (M1) and a second transistor (M2), whose gate...
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JP2004121625A |
To provide an arrangement for detecting a pulse wave which can measure a more exact pulse rate even when a processing means having a low calculation potential is used.An A/D conversion circuit 106 samples at 16Hz the pulse wave detected ...
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JP2004509503A |
Only a single, standard-independent clock rate is generated in a signal processor or a signal processing structure, and correspondingly only precisely one clock frequency generator is then arranged on the chip. The signal processing path...
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JP2004088679A |
To provide a duty ratio detection circuit in which a duty ratio is speedily corrected to shorten time of recovery from a current saving state to an ordinary state.A duty ratio detection circuit 30 is provided with: a detection circuit 21...
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JP3502607B2 |
A digital receiver for receiving DMT signals includes a time-domain equalizer that includes a digital filter having fixed coefficients.
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JP3473165B2 |
PURPOSE: To keep a clamp frequency constant without being influenced by a circuit constant and the like for converting it into voltage. CONSTITUTION: The period of the input pulse signal from a signal input terminal 1 is counted by a cou...
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JP2003318738A |
To realize a PWM device which can generate a PWM suitable for making an HDL IP and which can especially synthesize in a high-speed operation without problems and also to provide a design method therefor.1: An input terminal of an on-widt...
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JP3367728B2 |
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JP3366080B2 |
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JP2002319825A |
To provide an FM demodulation circuit that discriminates a high(H) or low(L) level of data demodulated by a simple configuration means so as to obtain the demodulation data with high discrimination accuracy.The FM demodulation circuit pr...
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JP2002232271A |
To provide a DC offset cancel circuit capable of canceling a DC offset voltage, which is generated in the differential output signal of a differential amplifier circuit, while preventing the distortion of a signal waveform caused by the ...
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JP2002223124A |
To solve the problem that a conventional frequency voltage conversion circuit has difficulty in keeping the linearity with respect to a frequency of a modulated signal to execute frequency voltage conversion when the center frequency is ...
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JP2002523959A |
A low IF receiver frequency translates an input signal in quadrature related mixers, filters in respective low pass channel filters, and derotates to produce a wanted signal and its image. At switch-on, the receiver is operated as a zero...
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JP3307527B2 |
To enable correct demodulation at all times even when a signal extending the received pulse width of a PPM signal almost double as wide as the original pulse width is inputted. A regenerative clock signal is extracted from a received PPM...
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JP3302032B2 |
PURPOSE: To eliminate the generation of an output voltage so that the influence of an offset voltages is always unmagnified even when an input frequency is 0Hz. CONSTITUTION: This frequency voltage is conversion circuit is provided with ...
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JP3303010B2 |
PURPOSE: To compensate for a loop for optimum stability and transition response by providing a pulse amplitude modulation means for selectively switching a shifted error voltage that passes through a twisted wire that is connected to an ...
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JP3300212B2 |
To reduce a circuit scale and power consumption by executing a bus boosting processing in a low sampling frequency when data is divided into frequency bands. Frequency-time base converters 6-1 to 6-3 input spectrum data which are divided...
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JP2002519989A |
Systems and methods can provide, in one aspect, a method for modulating the pulse width of control signals generated on a plurality of separate channels. In one practice, the methods described herein are suitable for execution on a micro...
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JP3295372B2 |
To reduce the device scale of a de-interleaving device and to simplify constitution. One word is composed of 32 bits and one block is composed of 32 words. Interleaved data obtained by sequentially and circularly dividing one block into ...
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JP3293857B2 |
PURPOSE: To prevent the deterioration in the response by multiplying a coefficient corresponding to a pulse train frequency with an analog voltage from an FVD with a different time constant and adding the products. CONSTITUTION: The conv...
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JP3290061B2 |
To improve the responsivity of a pulse counting circuit. A pulse counting circuit 11 counts input signals by an input signal counter 16, latches the signals with a latch 17 for each counting period which is set by a timer signal (B) from...
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JP3288835B2 |
PURPOSE: To provide a demodulator for a PDM wave capable of interpolating missing pulses of PDM waves (pulse density modulation waves) and a demodulator for a PDM wave interpolating missing pulses in a weak electric field in an FM recept...
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JP2001345677A |
To realize phase shift with stable delay time in a simple circuit.Transistors 12a and 12b are turned on and off by input signals in mutually opposite phases. By turning on the transistors 12a and 12b, capacitors 12a and 12b are discharge...
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JP3231318B2 |
1. A system consisting of a method and a preferred device suitable for carrying out the method according to the invention for time/voltage conversion is presented which determines voltage values which correspond to the duration of pulses...
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JP2001313534A |
To provide a manufacturing method for a capacitor incorporated piezoelectric resonator by which a soldering process can be simplified while downsizing is compatible.The manufacturing method for a capacitor incorporated piezoelectric reso...
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JP2001291296A |
To provide a duty decision circuit capable of varying a duty decision point. This circuit is provided with an up-down counter with codes which counts up/down with count clocks according to the high level/low level of input signals and an...
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JP3186718B2 |
To provide the carrier detection circuit that detects a carrier at a high speed while preventing mis-detection of the carrier. An RSSI block integration circuit 101 that receives an RSSI signal converted into a digital signal through A/D...
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JP3182164B2 |
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JP3176613B2 |
2.1 In known drive circuits, a separate semiconductor switch which can be switched on or off is allocated to each pixel electrode. 2.2 According to the invention, the drive circuit is operated in multiplex mode. In this mode, the sel...
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JP3177637B2 |
To shorten maximum operation time and to maintain the accuracy of m bit by representing m bit PWM signal with n pieces of sub-PWM signals (n is a common divisor of m), independently and operating in parallel each sub PWM signal with a pu...
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JP3102987B2 |
PURPOSE: To provide an offset compensation type pulse count detection circuit capable of compensating the influence on a demodulation signal that is the offset of a master clock frequency. CONSTITUTION: A phase comparator 8 detects phase...
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JP3088138B2 |
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JP3075846B2 |
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JP3060099B2 |
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JP2000183980A |
To provide a digital signal forming circuit to be used for a radio receiver of a time-division multiplex radio communication system for preventing its own communication from being made invalid due to interference generated due to the com...
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