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WO/2018/066377A1 |
The present invention addresses the problem of a temporally variable buffer gas shift in gas cells conventionally used in an atomic clock, the buffer gas shift being caused by the entry of He gas in the atmosphere into the gas cell, or b...
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WO/2018/067406A1 |
Apparatus and methods for frequency tuning of rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, distributed quantized tuning is used to tune a frequency of the RTWO. The RTWO includes a plurality o...
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WO/2018/067785A1 |
Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel...
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WO/2018/063231A1 |
For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the p...
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WO/2018/057262A1 |
An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wi...
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WO/2018/057153A1 |
Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which pha...
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WO/2018/057280A1 |
Various aspects of this disclosure describe switched-capacitor circuits in a PLL. Examples include routing current from a first current source through a capacitor to ground during a first clock phase, routing current from a second curren...
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WO/2018/049386A1 |
A delay generation circuit includes a modulator and a delay-locked loop. The delay-locked loop includes a delay line configured to be responsive to a phase difference between a first clock signal and one of a multitude of output signals ...
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WO/2018/047676A1 |
[Problem] To provide a gas-cell-type atomic oscillator that ensures high frequency stability over a long period of time. [Solution] The present invention provides an atomic oscillator that comprises: a first frequency synthesizer that sy...
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WO/2018/044432A1 |
Pulse generation circuitry includes edge generation circuitry and edge combination circuitry. The edge generation circuitry includes a first digital-to-time converter (DTC) configured to input a first phase signal that includes a first p...
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WO/2018/039538A1 |
Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequenc...
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WO/2018/034026A1 |
To obtain an oscillating signal with high spectral purity. An oscillation device 10 has: an oscillator 11; an erroneous frequency detection unit 12 which detects an erroneous frequency relative to a primary signal frequency output by the...
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WO/2018/032495A1 |
An analog computing device in time mode, comprising at least one multiplication unit (10), the multiplication unit (10) comprising: a digital-to-time converter (DTC), inputting a reference signal (Ref) and a digital signal M1, for output...
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WO/2018/028771A1 |
A fractional-N frequency synthesizer circuit (20, 20a-c) is disclosed. It comprises a frequency divider circuit (70) configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a diviso...
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WO/2018/022171A1 |
A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the pluralit...
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WO/2018/020605A1 |
The present invention facilitates phase control. A PFD (2) outputs a detection signal based on the phase difference or frequency difference between a reference signal (RCK) and a feedback signal (FB), a charge pump circuit (3) outputs a ...
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WO/2018/019342A1 |
The invention provides a method for providing a synchronization in a computer network for synchronized playback of audio an/or video by a plurality of separate devices. Each separate device generates a virtual clock in response to a timi...
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WO/2018/013406A1 |
A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the fi...
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WO/2018/012083A1 |
The present invention reduces a leak current while reducing low-frequency noise in an AGC circuit provided with a transistor that shifts to an on state or an off state according to the level of a signal. A switching circuit is provided w...
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WO/2018/012576A1 |
[Solution] A PLL unit (207-x) generates a sampling clock (Sd-x) on the basis of a word clock (W-x) (x = 0-n), and a PLL unit (207-y) generates a sampling clock (Sd-y) on the basis of a word clock (W-y) (x = 0-n, y≠x). When having the c...
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WO/2018/010732A2 |
The invention relates to a device (200) for controllably delaying an electrical signal, the device comprising: - a first signal transfer path (207) between a signal input (201) and a signal output (204), the path having -- a first signal...
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WO/2018/013241A1 |
A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit (100) includes an injection locked oscillator (102), a loop controller (116), and a phase interpolator (108). The inject...
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WO/2018/013327A1 |
A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage ...
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WO/2018/001526A1 |
A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and...
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WO/2018/000530A1 |
A calibration system and method for a voltage-controlled oscillator in a phase-locked loop. The calibration system comprises: a gain regulation unit which is connected to an input end of a voltage-controlled oscillator, and is used for i...
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WO/2018/001667A1 |
The invention relates to a method for synchronizing an inspection device (10), wherein the inspection device (10) is designed to test at least one first control device and the inspection device (10) comprises at least: one first computin...
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WO/2017/222620A1 |
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...
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WO/2017/220138A1 |
A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_1...PLL_N) and a plurality N of phase detectors (DET_1...DET_N). The plurality N of phase detectors and the plurality...
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WO/2017/218085A2 |
An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at ...
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WO/2017/213798A1 |
A method includes receiving an optical signal (20) through an optical link (22) and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving p...
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WO/2017/207932A1 |
The time arbitration circuit (1) includes: a comparator (2) including at least first and second inputs and configured to deliver at least one first piece of information (D) relating to the synchronisation state of the signals (C1, C2) pr...
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WO/2017/206075A1 |
Disclosed are a clock generator circuit and a clock signal generation method. The method comprises: using a direct current bias circuit in a first clock source, superimposing a first direct current voltage on a first clock signal output ...
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WO/2017/209986A1 |
An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further...
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WO/2017/204902A1 |
A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, su...
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WO/2017/198666A1 |
A MEMS resonator sensor uses a signal generator to generate first and second reference signals of the same frequency, wherein the first reference signal is used to drive a MEMS resonator. A digital controller is used for controlling the ...
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WO/2017/199603A1 |
A communication system according to the present disclosure is provided with: a transmission apparatus including a phase synchronization unit that is configured to generate a first clock signal and to be able to change a frequency of the ...
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WO/2017/197946A1 |
Disclosed is a PVTM-based, wide-voltage-range clock stretching circuit. The circuit comprises a PVTM circuit module, a phase clock generation module, a clock synchronization selection module, and a control module. The PVTM circuit module...
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WO/2017/195615A1 |
The present technology relates to a detection device and a detection method that enable a lock state to be determined more accurately. A first edge detector detects whether an edge of a second clock signal is present in one cycle of a fi...
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WO/2017/195614A1 |
The present invention relates to an oscillation circuit, an oscillation method, and a PLL circuit, whereby reduced power consumption and suppression of jitter (phase noise) degradation can be achieved at the same time. The oscillation ci...
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WO/2017/189160A1 |
A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local osci...
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WO/2017/185953A1 |
Provided is a digital frequency-division phase-locked loop, comprising: a time-to-digital converter, a digital loop filter, a digitally controlled oscillator, a feedback divider, a Sigma-Delta modulator and a correction device. The corre...
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WO/2017/185072A1 |
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a pluralit...
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WO/2017/184849A1 |
An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of...
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WO/2017/177864A1 |
A method and apparatus is described for estimating a local oscillator frequency offset (LOFO) of a received optical signal in a coherent optical receiver. The method includes receiving a signal by the coherent optical receiver; digitally...
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WO/2017/177585A1 |
Disclosed are a synchronously rotating reference frame phase-locked loop, and a test method and device therefor. The phase-locked loop comprises: a reference transformation module set to, according to a phase angle fed back by a phase-lo...
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WO/2017/177474A1 |
The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal； a primary control subsystem including a phase detector and a connection between the output signal and the phase...
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WO/2017/177064A1 |
An example clock generator circuit includes a fractional reference generator (202) configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a ...
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WO/2017/174142A1 |
A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter (1) to provide a digital control word (DFC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback ...
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WO/2017/177062A1 |
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signa...
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WO/2017/172219A1 |
A mobile communication device adapted to perform spur relocation for a digital phaselocked loop includes a receiver to determine a first frequency channel of interest and to identify a first frequency command word corresponding to the fi...
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