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WO/2021/126309A1 |
A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when an interpolator rollover event of a phase integer portion of a phase interpolator has occurred, an...
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WO/2021/120836A1 |
A frequency synthesizer, a frequency synthesis method, an electronic device and a storage medium. The frequency synthesizer comprises: a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency sy...
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WO/2021/125893A1 |
An apparatus and a method are provided for, in an electronic device which generates a reference signal having a reference frequency, mixes the reference signal to an input signal for transmission, and amplifies power, outputting a contro...
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WO/2021/121637A1 |
A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16...
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WO/2021/127146A1 |
A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in...
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WO/2021/121433A1 |
Provided are a phase-locked loop circuit, chip, circuit board, and electronic device, comprising a frequency and phase discriminator module (110), a charge pump module (120), a loop filter (130), a voltage-controlled oscillator (140) and...
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WO/2021/120617A1 |
A method for improving clock frequency coverage. The method comprises: performing signal frequency-division processing on an oscillator signal output by an oscillator in order to form a frequency division signal, wherein the number of ph...
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WO/2021/115701A1 |
The invention relates to a phase locked loop for a driver circuit for operating a MEMS gyroscope with a seismic mass which can be excited to oscillate, comprising an input interface for receiving position signals representing the current...
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WO/2021/114333A1 |
Disclosed is a circuit for reducing spurs in a local oscillator loop in a wireless communication comprehensive tester. The present invention provides a circuit for reducing spurs in a local oscillator loop in a wireless communication com...
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WO/2021/109508A1 |
Provided are a synchronous-machine-based synchronization system, a synchronization method and a calibration method for realizing the synchronous output of multiple signal sources from multiple channels. The synchronization system compris...
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WO/2021/112000A1 |
A DCO 200 is configured such that while a selection signal SEL is asserted, a ring oscillator is formed and the DCO 200 oscillates at a frequency according to a control code DCO_CODE, and while the selection signal SEL is negated, the DC...
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WO/2021/102927A1 |
Disclosed is a clock generation circuit, comprising a multi-phase clock generation circuit, an FM, a PD and a control circuit, wherein the multi-phase clock generation circuit is used for generating a multi-phase clock signal according t...
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WO/2021/108027A1 |
Aspects of the disclosure provide an apparatus that includes processing circuitry and a method for video decoding. The processing circuitry decodes coding information of a block to be reconstructed from a coded video bitstream. The codin...
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WO/2021/102678A1 |
A vibration control method, a terminal device, and a storage medium. The method comprises: acquiring a temperature of a terminal device (S101); determining a target frequency offset corresponding to the temperature (S102); and controllin...
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WO/2021/101605A1 |
A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate...
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WO/2021/098513A1 |
A frequency locking method for a phase-locked loop and a frequency locking circuit, relating to the technical field of a new generation of information, and mainly solving the technical problem that the locking time of an existing phase-l...
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WO/2021/092704A1 |
A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally ...
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WO/2021/094194A1 |
Circuit for modeling and emulating the pitch perception of complex sounds comprising: • a sample and hold circuit (2) arranged to receive and sample a quasi-periodic input signal (IN) comprising at least two predetermined frequencies (...
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WO/2021/097493A1 |
A digitally-controlled oscillator (DCO) is provided. In one aspect, the DCO includes a resonant tank that can include multiple inductors and multiple metal-oxide-semiconductor (MOS) transistors. The resonant tank can include a first circ...
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WO/2021/079563A1 |
A fractional phase-locked loop that multiplies the frequency of a reference signal by a non-integer and outputs a resultant signal to an output unit, comprises: a first frequency adjusting unit which controls the frequency of a signal to...
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WO/2021/077246A1 |
A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multip...
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WO/2021/080105A1 |
An apparatus for time synchronization of a relay apparatus, according to an embodiment of the present invention, comprises: a downlink reception unit for transmitting a downlink signal and a downlink transmission unit for forming a downl...
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WO/2021/076255A1 |
Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a...
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WO/2021/076685A1 |
In some embodiments, a molecular clock includes: a waveguide gas cell containing gas molecules having a rotational spectral line with a first frequency; a voltage-controlled oscillator (VCO) to generate a clock signal; a transmitter refe...
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WO/2021/068131A1 |
The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency wi...
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WO/2021/068326A1 |
Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, wherein the phase-lock acceleration circuit comprises a pulse width extraction control circuit and a current in...
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WO/2021/060787A1 |
Disclosed is an electronic device that is configured to determine whether a phase locked loop (PLL) circuit is operating normally, thereby preventing component damage in the electronic device and preventing disconnection from a communica...
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WO/2021/061575A1 |
A method and apparatus for enhancing the stability of an oscillator circuit by generating a comb of frequencies in a non-linear resonator member in response to a drive frequency, the oscillator circuit including a voltage controlled osci...
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WO/2021/055155A1 |
A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an ...
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WO/2021/047758A1 |
A time difference determining device determines a time difference between a first digital signal and a second digital signal. It comprises a first time difference determining branch, comprising a first delay line, in turn comprising N fi...
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WO/2021/049423A1 |
This atomic resonator 10 comprises: a gas cell 1 in which alkali metal atoms have been enclosed; a light detection device 2 that detects light that has traversed the gas cell 1 and converts said light into an electric signal; a high freq...
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WO/2021/042266A1 |
An asynchronous sampling architecture (100) and a chip. The asynchronous sampling architecture (100) is used for receiving a first input data string (dl) from the opposite end, and comprises: a first register (102) used for caching the f...
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WO/2021/036274A1 |
Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, wherein same belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises:...
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WO/2021/036518A1 |
Disclosed is a fast-locking phase-locked loop circuit for avoiding a cycle slip, wherein same belongs to the technical field of integrated circuits. The fast-locking phase-locked loop circuit comprises: a phase frequency detector, a char...
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WO/2021/036805A1 |
A signal generation circuit, a signal generation method, a digital time conversion circuit and a digital time conversion method. The signal generation circuit comprises: a first generation circuit configured to generate a periodic first ...
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WO/2021/036775A1 |
A signal generation circuit, a signal generation method, a digital-to-time conversion circuit, and a digital-to-time conversion method. The signal generation circuit comprises: a first generation circuit configured to generate a periodic...
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WO/2021/035166A1 |
A temperature insensitive oscillator system. The system includes a substrate having a first surface and an opposing second surface, a CMOS device with one or more CMOS circuits attached to the first surface of the substrate, one or more ...
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WO/2021/029959A1 |
A method and corresponding system of determining a property of a particle, comprising: flowing the particle in a device comprising a suspended microchannel resonator, the suspended microchannel resonator comprising a microfluidic channel...
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WO/2021/026658A1 |
An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mod...
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WO/2021/026657A1 |
A delay device includes a tuning network including first and second tuning components having frequency responses that overlap in an intermediate frequency band to provide a group delay response. A delay modifier is in communication with ...
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WO/2021/024619A1 |
Provided is an atomic cell glass that can make it difficult for a change in oscillation frequency to occur over time in an atomic oscillator. This atomic cell glass is a glass for use in atomic cells, and has a density of 2.4 g/cm3 or ...
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WO/2021/025820A1 |
Phase variations between a transmitter (TX) waveform and a receiver (RX) waveform produced by a TX Phase-Locked-Loop (PLL) and a RX PLL, respectively, is a source of error in processing delay calibration used, e.g., in Round Trip Time (R...
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WO/2021/024345A1 |
A first phase adjuster (11) adjusts the phase of either a first or second AC voltage (V1, V2) generated in a negative resistance circuit (10), such that the shift amount φ in a first variable phase shifter (12) is kept within the range ...
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WO/2021/021250A1 |
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other bene...
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WO/2021/016740A1 |
Disclosed are a single-phase adaptive phase-locked apparatus and method. The single-phase adaptive phase-locked apparatus comprises: a phase detector, a proportional-integral controller, a dynamic wave trap, and a voltage-controlled osci...
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WO/2021/021704A1 |
A device (100) includes a clock generator (106) configured to generate a root clock signal (MCLK) based on an input clock signal (CLK) and a clock generator divider integer setting. The device (100) also includes a first component (112A)...
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WO/2021/016085A1 |
Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part o...
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WO/2021/011270A1 |
Apparatus, methods, and computer-readable media for facilitating beam-based sequence spaces for synchronization signals are disclosed herein. An example method for wireless communication for a first device includes selecting a subset of ...
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WO/2021/011830A1 |
Methods, devices and systems for providing accurate measurements of timing errors using optical techniques are described. An example timing measurement device includes an optical hybrid that receives two optical pulse trains and produces...
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WO/2021/011955A1 |
A system, circuit (750, 1550) and method (1700) for providing a controlled oscillator frequency with reduced phase noise for use in a communication system. In one embodiment, the circuit (750, 1550) includes a delay line (775, 1575) coup...
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