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Matches 1 - 50 out of 31,084

Document Document Title
WO/2018/189288A1
An asynchronous state machine (30) for a phase/frequency detector (12) operative in a phase locked loop (10) includes a short pulse suppression circuit (40, 50, 60, 70, 80) operative to suppress output pulses of duration on the order of ...  
WO/2018/186876A1
Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, s...  
WO/2018/187335A1
Some embodiments include apparatuses and methods of operating such apparatuses. One of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an input clock signal and a feedback clock signal, and to ge...  
WO/2018/179920A1
[Problem] To control delay time with high accuracy. [Solution] A delayed locked loop circuit provided with: a first delay circuit that comprises at least one first delay device and at least one second delay device, the first delay device...  
WO/2018/182918A1
Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending ...  
WO/2018/177195A1
A charge pump (1), a charge pump-based processing method and phase-locked loop circuit, and a storage medium. The charge pump comprises a charge pump main circuit (11), a common-mode feedback circuit (12), and a voltage bias circuit (13)...  
WO/2018/175194A2
An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mi...  
WO/2018/171141A1
The present invention relates to a single phase voltage digital phase locking method, and a preset level signal similar to a voltage signal to be measured is constructed. In the control process, according to an angular frequency obtained...  
WO/2018/166130A1
Disclosed are a duty cycle adjustment apparatus and method. The apparatus comprises: a first edge extraction unit (1) for extracting a rising edge of a first clock signal; a lock determination unit (2), with an input end connected to the...  
WO/2018/169561A1
A microfluidic device molded in a single step provides a seamless fluid communication path from fluid input features to microfluidic channels. The device comprises a molded material which is formed around thread for forming high aspect r...  
WO/2018/169653A1
An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and seco...  
WO/2018/164828A1
A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a freq...  
WO/2018/163405A1
An IQ signal source (100) provided with: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the first VCO (1) and the second VCO (2) electrically coupling to thereby output an I signal and a Q signal; a first PLL (10) for comparing...  
WO/2018/162987A1
Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop ("PLL") wherein the holdover PLL is configured to perform a holdover function by receiving a system cl...  
WO/2018/157926A1
A system (200) for phase control of a Phased Locked Loop, PLL, is disclosed. The system comprises said PLL. Said PLL comprises an oscillator (210) configured to generate an output signal; a frequency divider (220) configured to generate ...  
WO/2018/158614A1
A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital conv...  
WO/2018/160578A1
Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a powe...  
WO/2018/149595A1
The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320).The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a c...  
WO/2018/151874A1
Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled...  
WO/2018/145326A1
A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO) (40). A digital data modulation signal is combined with a carrier and input to a feedback divider (52). The data modulation signal i...  
WO/2018/145759A1
A differential electronic circuit (25) comprising a tuning circuit (140, 140-i) connected between a first circuit node (110) and a second circuit node (112) of the electronic circuit (25), is disclosed. The tuning circuit (140, 140-i) co...  
WO/2018/146896A1
A multiband control oscillation unit (23, 223) is provided with a plurality of bands in which frequency is gradually increased or gradually decreased in accordance with a control signal (Vc) apart from each other, and configured such tha...  
WO/2018/145318A1
A Phase-Locked Loop (PLL) has a multi-curve voltage-controlled oscillator (VCO) with a curve-select input that adjusts the capacitance within the VCO and thus the VCO gain. A calibration unit generates a curve-select value to the VCO. Co...  
WO/2018/145612A1
A charge pump circuit and a phase-locked loop, the circuit comprising a start module (10), a bias module (20), a current mirror module (30), a charging and discharging feedback control module (40) and a charging and discharging matching ...  
WO/2018/144207A1
Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit include...  
WO/2018/144115A1
A test set system and related method are provided comprise a first direct digital synthesizer (DDS) having a balanced output configured to produce a first signal, and a second DDS having a balanced output signal configured to produce a s...  
WO/2018/140263A1
Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch couple...  
WO/2018/132110A1
System for determining periodic values of phase angle Φ of waveform power input including voltage detector for detecting periodic values of average voltage of waveform power input and detecting corresponding periodic values of peak volt...  
WO/2018/131084A1
With a conventional PLL circuit, circuit characteristics change dynamically due to temperature changes and degradation over time, and therefore there was the problem that it was difficult to find suitable application parameters for DAC. ...  
WO/2018/130025A1
An alkali-metal vapor cell atomic clock system, comprising a first atomic vapor cell (140) and a second atomic vapor cell (150). A digital signal processor (170) outputs a first timing sequence to control a first laser signal, and the di...  
WO/2018/126800A1
The present invention discloses a low-phase-noise frequency synthesizer. The synthesizer comprises a reference crystal oscillator configured to generate a reference signal. The reference crystal oscillator is connected to a power distrib...  
WO/2018/126720A1
A numerically-controlled oscillator comprises: a frequency divider chain, configured to perform frequency division on an input clock signal to generate K fundamental clock signals, and feeding the K fundamental clock signals to a time av...  
WO/2018/126706A1
The present disclosure relates to a frequency-tunable frequency source and system, method and electronic apparatus related thereto, and in particular to a frequency-tunable frequency source having an input terminal for receiving an input...  
WO/2018/125046A1
A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase diff...  
WO/2018/125364A1
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quan...  
WO/2018/125232A1
Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry ...  
WO/2018/126142A1
A system (100) (and associated method) includes an input flip-flop (120), a counter (130), and a clock tree (110). The input flip-flop (120) includes a clock input terminal configured to be coupled to a device clock (90), or a clock gene...  
WO/2018/124506A1
The present invention relates to a design technique for a phase locked loop (PLL) that produces an accurate clock frequency in a clock synchronization system. The present invention proposes a hardware description language (HDL)-based new...  
WO/2018/125594A1
A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to th...  
WO/2018/125469A1
A phase-locked loop circuit includes (a) a phase frequency detector which receives the input signal of the phase-locked loop and a feedback signal that is derived from the output signal of the phase-locked loop, the phase-frequency detec...  
WO/2018/121187A1
According to a first example aspect there is provided a charge pump circuit that includes a first chopper circuit configured to switch first and second chopper circuit outputs between first and second chopper circuit inputs at a chopping...  
WO/2018/125399A1
A method is described. The method includes periodically maintaining memory devices with circuitry of a memory controller. The circuitry is to act in response to signals from timer and scheduling circuitry that determine when memory maint...  
WO/2018/123199A1
A frequency divider control circuit (15) outputs, to a frequency divider (14), a frequency divider control signal for increasing a frequency division ratio N from a first frequency division ratio to a second frequency division ratio larg...  
WO/2018/118274A1
A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference sign...  
WO/2018/118034A1
An electromagnetic energy delivery system includes a set of radio frequency channels; each channel configured to receive a set of reference signals. Each channel further includes a compensation component and a phase-locked loop component...  
WO/2018/113668A1
A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and a...  
WO/2018/116347A1
A first frequency accumulator (7a) operates using, as a clock, an output signal of a variable frequency divider (3). A second frequency accumulator (7b) operates using, as a clock, a reference signal transmitted from a reference signal s...  
WO/2018/113903A1
Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a PhaseLocked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a ...  
WO/2018/111413A1
A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a...  
WO/2018/109898A1
According to the present invention, a lock detector (8) detects an unlock state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal when the unlock state is detected in the lock detector (8). A par...  

Matches 1 - 50 out of 31,084