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Matches 1 - 50 out of 31,423

Document Document Title
WO/2019/210473A1
Provided are a clock data recovery apparatus, an optical line terminal and a passive optical communication system. The clock data recovery apparatus comprises: a phase detection loop unit, a frequency oscillation unit, a frequency detect...  
WO/2019/212662A1
Exemplary systems, apparatus, and methods described herein may improve a scan process for near field communications, such as IEEE 802.15.4. The improvements may include, during the scan process, performing one of increasing a current of ...  
WO/2019/213654A1
A time-to-digital converter circuit (100) includes a logic gate (130) configured to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate (130) i...  
WO/2019/209495A1
A resonance system is disclosed, which includes a first resonance device configured to receive a drive signal and generate an output signal, a second resonance device configured to receive a control signal and generate the drive signal b...  
WO/2019/205177A1
A phase locked loop, comprising: an oscillator; a digital switch capacitor array connected in parallel to a varactor in the oscillator, the digital switch capacitor array comprising N switch capacitors connected in parallel, and N being ...  
WO/2019/201260A1
A local oscillator (LO) distribution system is described. The LO system includes a plurality of phase-locked loop (PLL) modules coupled to each other in a one-way, circulant coupling topology. Each PLL module receives a reference clock s...  
WO/2019/191895A1
Provided are a phase-locked loop and a terminal device. The phase-locked loop comprises: a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator. The phase detector is connected to the low-pass filter by m...  
WO/2019/190567A1
A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than...  
WO/2019/183866A1
A frequency generator, comprising a control unit for receiving an input signal to generate a divisor signal, a phase signal and a cycle signal; a frequency divider for receiving the input signal, and performing integer frequency division...  
WO/2019/132802A3
The present invention is a system for realizing band calibration of a voltage controlled oscillator (100) which generates signal having cycle frequency which is proportional with a control value in a control signal received as input, cha...  
WO/2019/190558A1
Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock l...  
WO/2019/191455A1
Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase e...  
WO/2019/185054A1
A frequency multiplier, a digital phase lock loop circuit and a frequency multiplying method. The frequency multiplier comprises: a clock controller for receiving an output signal from a time-to-digital converter in a digital phase lock ...  
WO/2019/183943A1
Provided in an embodiment of the present invention are an automatic amplitude control device and method. The device comprises: an oscillator and a current source array, wherein one terminal of the current source array is coupled with a s...  
WO/2019/188990A1
[Problem] To provide a technique, with respect to an oscillating device that uses a crystal oscillator and stabilizes an oscillating frequency on the basis of an external clock signal, for stabilizing the oscillating frequency that is ou...  
WO/2019/182642A1
A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an ana...  
WO/2019/182697A1
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more...  
WO/2019/178748A1
A frequency generator. The frequency generator comprises a sigma-delta modulator for generating a divisor control signal and a phase control signal; an oscillator for generating an oscillation signal, the oscillation signal having a firs...  
WO/2019/178174A1
A phase-locked loop (PLL) includes a selection circuit (102) including multiple inputs, each input to receive a separate reference clock. A programmable reference clock divider (104) divides down the reference clock selected by the selec...  
WO/2019/178176A1
A phase-locked loop (PLL) system (100) includes a first PLL (170) coupled to receive a first reference clock. The PLL system (100) also includes a second PLL (140) coupled to receive a second reference clock. The output of the second PLL...  
WO/2019/177532A1
A divider synchronization device (100) is disclosed, which comprises at least first and second circuit portions (102, 104) configured to generate respective radio signals for multichannel transmission, each circuit portion having a proce...  
WO/2019/177945A1
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler (202) configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data ...  
WO/2019/171585A1
A first pulse selector (7a) outputs an output signal of a variable frequency divider (3) to phase frequency comparators (4a-4d) in a time divisional manner. A second pulse selector (7b) outputs a reference signal from a reference signal ...  
WO/2019/171607A1
The purpose of the present invention is to provide an oscillation device which achieves both expansion of frequency variable width and refinement of the variable pitch thereof. An oscillation device 1 is provided with: an oscillation uni...  
WO/2019/173821A1
A circuit includes a time-to-digital converter (TDC) (102) to produce an output signal that is a function of a time difference between a first input clock to the TDC (102) and a second input clock to the TDC (102). A first delay line (50...  
WO/2019/172467A1
A phase-locked loop (PLL) apparatus and a method for clock synchronization are disclosed. According to an embodiment, the PLL apparatus comprises an adjustable oscillator, one or more first difference determiners, one or more first param...  
WO/2019/169607A1
A charge pump circuit for suppressing current mismatch and a control method therefor, and a phase locked loop circuit, relating to the technical field of communications. The charge pump circuit comprises: a first control circuit (10), a ...  
WO/2019/167670A1
The present art relates to a phase-locked loop circuit that enables power consumption to be reduced. The phase-locked loop circuit comprises: an SAR-ADC that includes two capacitors and outputs a comparison result of voltages occurring a...  
WO/2019/168452A1
Embodiments of the present disclosure provide methods and apparatus for demodulating a received signal. For example, a demodulation system for demodulating an input signal is provided. The input signal comprises a carrier wave modulated ...  
WO/2019/164625A1
An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit t...  
WO/2019/156422A1
An integrated circuit according to one embodiment disclosed herein comprises: a plurality of functional blocks; a spread spectrum clock (SSC) generator for generating an SSC on the basis of a frequency modulation rate value; a clock dist...  
WO/2019/153810A1
Provided are a signal transmission method, a driver and a system. The driver comprises: the data channel circuit, which is used for implementing equalization-processing-based transparent signal transmission between a first communication ...  
WO/2019/150942A1
This technology relates to a charge pump circuit that allows the circuit area to be reduced. Provided is a charge pump circuit comprising: a first transistor; a second transistor supplied with a constant current; a third transistor conne...  
WO/2019/148126A1
Methods and systems are described for receiving, over a plurality of consecutive signaling intervals, a plurality of codewords, each codeword received as a plurality of symbols via wires of a multi-wire bus, the plurality of symbols rece...  
WO/2019/148014A1
Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of...  
WO/2019/144671A1
A method for measuring the stability of a phase locked loop within a central processing unit by using a frequency meter, comprising: the central processing unit outputting an oscillation excitation signal to a crystal circuit; the crysta...  
WO/2019/146177A1
According to the present invention, power consumption is suppressed in a time-to-digital converting circuit (TDC) used in a phase-locked loop. The time-to-digital converting circuit is provided with an analog-to-digital converting circui...  
WO/2019/141584A1
An oscillator circuit arrangement comprises a gain stage (10) and a feedback loop that includes a crystal device (XC). A clock signal monitor circuit(12) is connected to an output (102) of the gain stage and detects a frequency shift in ...  
WO/2019/133985A1
A clock apparatus (100) includes a gas cell (102), which includes: (a) a first chamber (104) including a sealed interior for providing a signal waveguide; and (b) a second chamber (106), in fluid communication with the first chamber, and...  
WO/2019/133983A1
A clock apparatus (101) includes: (a) a gas cell (12), including a cavity including a sealed interior for providing a signal waveguide; (b) a first apparatus (ANTXPROBE) for providing a first electromagnetic wave to travel in the cavity ...  
WO/2019/127054A1
Disclosed in the present invention is a frequency generating apparatus, comprising: a reference frequency generating circuit used for producing a reference frequency; a frequency synthesising circuit connected to the reference frequency ...  
WO/2019/127537A1
A wideband low-phase-noise frequency synthesizer circuit and an electronic device. The frequency synthesizer circuit comprises: an oscillation circuit (10) outputting first and second oscillation frequencies; a feedback circuit (30) and ...  
WO/2019/133984A1
A clock apparatus (101) includes: (a) a gas cell (12), including a continuous path cavity including a sealed interior for providing a signal waveguide; (b) an apparatus (14) for providing an electromagnetic wave to travel along the conti...  
WO/2019/132802A2
The present invention is a system for realizing band calibration of a voltage controlled oscillator (100) which generates signal having cycle frequency which is proportional with a control value in a control signal received as input, cha...  
WO/2019/122792A1
The method (100) for temporal synchronization of devices communicating on a data network comprises: - a step (105) of sending, by a primary device, referred to as the "time server," a temporal synchronization signal, - a step (110) of re...  
WO/2018/215991A8
A Phase-locked loop circuit including: a local oscillator (14), configured to generate a timing signal (VLO); a variable- length shift register (19), controlled by the timing signal; and a feedback control circuit (2, 18, 20, 22, 24, 26)...  
WO/2019/125300A1
A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit (200) is disclosed, which comprises: a DTC error compensator (202) arranged to receive a phase offset signal being a processed output from a time- t...  
WO/2019/125869A1
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate...  
WO/2019/125679A1
A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A ma...  
WO/2019/125534A1
A level transmitter (500) includes an analog-to-digital convertor clock signal generator (504) that receives a transmitter clock signal that is used to establish when an incident signal is transmitted toward a material boundary (122, 124...  

Matches 1 - 50 out of 31,423