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Matches 1 - 50 out of 31,002

Document Document Title
WO/2018/132110A1
System for determining periodic values of phase angle Φ of waveform power input including voltage detector for detecting periodic values of average voltage of waveform power input and detecting corresponding periodic values of peak volt...  
WO/2018/131084A1
With a conventional PLL circuit, circuit characteristics change dynamically due to temperature changes and degradation over time, and therefore there was the problem that it was difficult to find suitable application parameters for DAC. ...  
WO/2018/130025A1
An alkali-metal vapor cell atomic clock system, comprising a first atomic vapor cell (140) and a second atomic vapor cell (150). A digital signal processor (170) outputs a first timing sequence to control a first laser signal, and the di...  
WO/2018/126800A1
The present invention discloses a low-phase-noise frequency synthesizer. The synthesizer comprises a reference crystal oscillator configured to generate a reference signal. The reference crystal oscillator is connected to a power distrib...  
WO/2018/126720A1
A numerically-controlled oscillator comprises: a frequency divider chain, configured to perform frequency division on an input clock signal to generate K fundamental clock signals, and feeding the K fundamental clock signals to a time av...  
WO/2018/126706A1
The present disclosure relates to a frequency-tunable frequency source and system, method and electronic apparatus related thereto, and in particular to a frequency-tunable frequency source having an input terminal for receiving an input...  
WO/2018/125046A1
A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase diff...  
WO/2018/125364A1
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quan...  
WO/2018/125232A1
Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry ...  
WO/2018/126142A1
A system (100) (and associated method) includes an input flip-flop (120), a counter (130), and a clock tree (110). The input flip-flop (120) includes a clock input terminal configured to be coupled to a device clock (90), or a clock gene...  
WO/2018/124506A1
The present invention relates to a design technique for a phase locked loop (PLL) that produces an accurate clock frequency in a clock synchronization system. The present invention proposes a hardware description language (HDL)-based new...  
WO/2018/125594A1
A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to th...  
WO/2018/125469A1
A phase-locked loop circuit includes (a) a phase frequency detector which receives the input signal of the phase-locked loop and a feedback signal that is derived from the output signal of the phase-locked loop, the phase-frequency detec...  
WO/2018/121187A1
According to a first example aspect there is provided a charge pump circuit that includes a first chopper circuit configured to switch first and second chopper circuit outputs between first and second chopper circuit inputs at a chopping...  
WO/2018/125399A1
A method is described. The method includes periodically maintaining memory devices with circuitry of a memory controller. The circuitry is to act in response to signals from timer and scheduling circuitry that determine when memory maint...  
WO/2018/123199A1
A frequency divider control circuit (15) outputs, to a frequency divider (14), a frequency divider control signal for increasing a frequency division ratio N from a first frequency division ratio to a second frequency division ratio larg...  
WO/2018/118274A1
A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference sign...  
WO/2018/118034A1
An electromagnetic energy delivery system includes a set of radio frequency channels; each channel configured to receive a set of reference signals. Each channel further includes a compensation component and a phase-locked loop component...  
WO/2018/113668A1
A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and a...  
WO/2018/116347A1
A first frequency accumulator (7a) operates using, as a clock, an output signal of a variable frequency divider (3). A second frequency accumulator (7b) operates using, as a clock, a reference signal transmitted from a reference signal s...  
WO/2018/113903A1
Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a PhaseLocked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a ...  
WO/2018/111413A1
A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a...  
WO/2018/109898A1
According to the present invention, a lock detector (8) detects an unlock state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal when the unlock state is detected in the lock detector (8). A par...  
WO/2018/111440A1
Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clo...  
WO/2018/108288A1
A phase interpolator (100) to receive a first and a second input clock (110, 120) with a first and a second input clock edge (111, 121) comprises an interpolating circuit unit comprising: resistors (153a, 153b) in parallel; for each resi...  
WO/2018/106778A1
An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined...  
WO/2018/106178A1
Method for synchronization of a data communications network including a plurality of node devices (n0-n4) which are interconnected through a coaxial network and configured for data communication within a predetermined frequency bandwidth...  
WO/2018/096730A1
The purpose of the present invention is to provide: an atomic oscillator that either does not require a dimming filter at all, or at the least does not require a dimming filter having high dimming characteristics; and an electronic devic...  
WO/2018/090686A1
Provided is a frequency synthesizer, comprising a phase-locked loop module (10), a loop filter (20) and a voltage-controlled oscillator module (30). The voltage-controlled oscillator module (30) comprises a plurality of voltage-controlle...  
WO/2018/090037A1
Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response ...  
WO/2018/082300A1
Provided are a wireless transmitter and a control method therefor, and a computer storage medium. The wireless transmitter comprises a phase lock module and a power amplifier, wherein the phase lock module is configured to perform up-fre...  
WO/2018/080687A1
One aspect of the present disclosure relates to a method for operating a charge pump. The method includes comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, a...  
WO/2018/080696A1
A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in...  
WO/2018/077719A1
In an embodiment an oscillator circuit comprises a first integrator-comparator unit (100), a second integrator- comparator unit (200), and a logic circuit (300). The first integrator-comparator unit (100) is prepared to provide a first s...  
WO/2018/072836A1
An oscillator (10) is provided. The oscillator (10) is configured for generating an output signal (24) which is phase locked to an input signal (20). The oscillator (10) comprises a controlled oscillator (15) configured for generating th...  
WO/2018/074031A1
The purpose of the present invention is to provide a highly accurate atomic oscillator and an electronic device having an atomic oscillator in which an obtained EIT signal has a thinner line width. An atomic oscillator (100) according to...  
WO/2018/075064A1
A phase locked loop arrangement is disclosed and includes a loop filter, an output combiner, an oscillator and a feedback path. The loop filter is configured to apply a proportional gain to an error signal to generate a loop signal. The ...  
WO/2018/073562A1
An apparatus for synchronizing an input signal (D) that is asynchronous to a clock signal (CLK) received by the apparatus. The apparatus comprising selection circuitry (104) configured to select the input signal and to generate a pair of...  
WO/2018/072449A1
The present invention relates to a two-point modulation transmitter calibration circuit and a calibration method. The circuit comprises: a two-point modulation phase locked loop system, a signal input circuit, a power amplifier and a gai...  
WO/2018/066377A1
The present invention addresses the problem of a temporally variable buffer gas shift in gas cells conventionally used in an atomic clock, the buffer gas shift being caused by the entry of He gas in the atmosphere into the gas cell, or b...  
WO/2018/067406A1
Apparatus and methods for frequency tuning of rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, distributed quantized tuning is used to tune a frequency of the RTWO. The RTWO includes a plurality o...  
WO/2018/067785A1
Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel...  
WO/2018/063231A1
For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the p...  
WO/2018/057262A1
An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wi...  
WO/2018/057153A1
Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which pha...  
WO/2018/057280A1
Various aspects of this disclosure describe switched-capacitor circuits in a PLL. Examples include routing current from a first current source through a capacitor to ground during a first clock phase, routing current from a second curren...  
WO/2018/049386A1
A delay generation circuit includes a modulator and a delay-locked loop. The delay-locked loop includes a delay line configured to be responsive to a phase difference between a first clock signal and one of a multitude of output signals ...  
WO/2018/047676A1
[Problem] To provide a gas-cell-type atomic oscillator that ensures high frequency stability over a long period of time. [Solution] The present invention provides an atomic oscillator that comprises: a first frequency synthesizer that sy...  
WO/2018/044432A1
Pulse generation circuitry includes edge generation circuitry and edge combination circuitry. The edge generation circuitry includes a first digital-to-time converter (DTC) configured to input a first phase signal that includes a first p...  
WO/2018/039538A1
Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequenc...  

Matches 1 - 50 out of 31,002