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Matches 1 - 50 out of 31,343

Document Document Title
WO/2019/156422A1
An integrated circuit according to one embodiment disclosed herein comprises: a plurality of functional blocks; a spread spectrum clock (SSC) generator for generating an SSC on the basis of a frequency modulation rate value; a clock dist...  
WO/2019/153810A1
Provided are a signal transmission method, a driver and a system. The driver comprises: the data channel circuit, which is used for implementing equalization-processing-based transparent signal transmission between a first communication ...  
WO/2019/150942A1
This technology relates to a charge pump circuit that allows the circuit area to be reduced. Provided is a charge pump circuit comprising: a first transistor; a second transistor supplied with a constant current; a third transistor conne...  
WO/2019/148126A1
Methods and systems are described for receiving, over a plurality of consecutive signaling intervals, a plurality of codewords, each codeword received as a plurality of symbols via wires of a multi-wire bus, the plurality of symbols rece...  
WO/2019/148014A1
Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of...  
WO/2019/144671A1
A method for measuring the stability of a phase locked loop within a central processing unit by using a frequency meter, comprising: the central processing unit outputting an oscillation excitation signal to a crystal circuit; the crysta...  
WO/2019/146177A1
According to the present invention, power consumption is suppressed in a time-to-digital converting circuit (TDC) used in a phase-locked loop. The time-to-digital converting circuit is provided with an analog-to-digital converting circui...  
WO/2019/141584A1
An oscillator circuit arrangement comprises a gain stage (10) and a feedback loop that includes a crystal device (XC). A clock signal monitor circuit(12) is connected to an output (102) of the gain stage and detects a frequency shift in ...  
WO/2019/133985A1
A clock apparatus (100) includes a gas cell (102), which includes: (a) a first chamber (104) including a sealed interior for providing a signal waveguide; and (b) a second chamber (106), in fluid communication with the first chamber, and...  
WO/2019/133983A1
A clock apparatus (101) includes: (a) a gas cell (12), including a cavity including a sealed interior for providing a signal waveguide; (b) a first apparatus (ANTXPROBE) for providing a first electromagnetic wave to travel in the cavity ...  
WO/2019/127054A1
Disclosed in the present invention is a frequency generating apparatus, comprising: a reference frequency generating circuit used for producing a reference frequency; a frequency synthesising circuit connected to the reference frequency ...  
WO/2019/127537A1
A wideband low-phase-noise frequency synthesizer circuit and an electronic device. The frequency synthesizer circuit comprises: an oscillation circuit (10) outputting first and second oscillation frequencies; a feedback circuit (30) and ...  
WO/2019/133984A1
A clock apparatus (101) includes: (a) a gas cell (12), including a continuous path cavity including a sealed interior for providing a signal waveguide; (b) an apparatus (14) for providing an electromagnetic wave to travel along the conti...  
WO/2019/132802A2
The present invention is a system for realizing band calibration of a voltage controlled oscillator (100) which generates signal having cycle frequency which is proportional with a control value in a control signal received as input, cha...  
WO/2019/122792A1
The method (100) for temporal synchronization of devices communicating on a data network comprises: - a step (105) of sending, by a primary device, referred to as the "time server," a temporal synchronization signal, - a step (110) of re...  
WO/2018/215991A8
A Phase-locked loop circuit including: a local oscillator (14), configured to generate a timing signal (VLO); a variable- length shift register (19), controlled by the timing signal; and a feedback control circuit (2, 18, 20, 22, 24, 26)...  
WO/2019/125300A1
A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit (200) is disclosed, which comprises: a DTC error compensator (202) arranged to receive a phase offset signal being a processed output from a time- t...  
WO/2019/125869A1
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate...  
WO/2019/125679A1
A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A ma...  
WO/2019/125534A1
A level transmitter (500) includes an analog-to-digital convertor clock signal generator (504) that receives a transmitter clock signal that is used to establish when an incident signal is transmitted toward a material boundary (122, 124...  
WO/2019/126274A1
Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first ...  
WO/2019/117932A1
An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of t...  
WO/2019/114449A1
The present invention provides a method for calibrating a crystal frequency deviation by means of an internal loop of a central processing unit (CPU). The method comprises: the CPU outputs an oscillating excitation signal to a crystal ci...  
WO/2019/118485A1
Described examples include a gas cell (201), including a cavity (203) in a first substrate (202), a nonvolatile precursor material in the cavity (203), and a second substrate (206) bonded to the first substrate (202) to seal the cavity (...  
WO/2019/111554A1
[Problem] To provide a serial data transmission device which, when a plurality of data transmission devices are daisy-chained and serial data is transmitted, is able to dynamically switch a band and a data transmission path while perform...  
WO/2019/109356A1
A clock system (100). The clock system (100) comprises a reference clock module (110), a phase-locked loop module (120), a phase-locked loop power source module (130), a phase-locked loop fault detection module (140) and a phase-locked l...  
WO/2019/100284A1
A phase locking method, apparatus and device. The method comprises: circularly sampling power grid voltage information in a quarter cycle of a power grid voltage signal wave; setting an array with the length of L, L being jointly determi...  
WO/2018/089121A3
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2019/096772A1
A phase-locked loop circuitry (200) having low variation transconductance design comprises a voltage controlled oscillator structure (308) to provide an output signal (Fosc) having an oscillation frequency. The voltage controlled oscilla...  
WO/2019/094509A1
A signal generator. A voltage controlled oscillator generates a signal that is fed to a comb generator, e.g., a nonlinear transmission line. A tone, from among a comb of tones at the output of the comb generator, is selected by a bandpas...  
WO/2019/091246A1
A method for regulating the frequency division of a phase-locked loop (PLL), which is applied in an embedded system: (S1) acquiring multiple corresponding frequency division points according to a default frequency division value of a PLL...  
WO/2019/092440A1
A circuit portion (100) is provided which comprises a phase expansion portion (111) arranged to receive an oscillating input signal (202) with a first frequency and output a first digital signal (206) having a plurality of parts each hav...  
WO/2019/090127A1
Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (...  
WO/2019/089791A1
A fractional clock generator (104) includes a full quadrant analog interpolator (206). A quadrature clock signal (202) with minimal jitter is provided to the full quadrant analog interpolator (206). The full quadrant analog interpolator ...  
WO/2019/084645A1
The present invention describes a method and a product for chemical equalisation based on the transmission of frequencies that act on the equalisation of chemical elements or substances, consequently adjusting the strengthening or weaken...  
WO/2019/083878A1
Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an...  
WO/2019/077673A1
The present invention addresses the problem of a conventional signal source that the noise of a VCO control voltage increases and the phase noise of an output signal of the signal source degrades. A signal source according to the present...  
WO/2019/079517A1
A computer system for automating the shifting of pixels within a digital video receives a first starting point through a user interface. The first starting point is received through a user selection of a first beginning portion of a vide...  
WO/2019/078993A1
A rail-to-rail sense amplifier includes a PMOS differential pair and an NMOS differential pair (Ml, M2) that are arranged in parallel with regard to a biasing network for driving a class AB output stage (M4, P4). The sense amplifier incl...  
WO/2019/057537A3
There are provided examples of receivers, controller units (e.g., for the receivers) and related methods (e.g. for the receivers). One receiver is provided which comprises: an adjustable sample provider (604) configured to provide sample...  
WO/2019/073841A1
This phase locked loop is provided with: a phase comparison circuit that compares the phase of a first signal and the phase of a second signal corresponding to a clock signal; a loop filter that comprises a resistive element having one e...  
WO/2019/075414A1
Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to ...  
WO/2019/071939A1
Various arrangements for decreasing harmonics of an output digital signal are presented. A programmable current rise-time circuit may be present that controls a rising edge of the output digital signal, wherein the output digital signal ...  
WO/2019/074727A1
An example digital-to-time converter (DTC) (102) includes: a delay chain circuit (301) having a plurality of delay cells (302) coupled in sequence, the delay chain circuit including a first input (Fref) to receive a first clock signal an...  
WO/2019/062224A1
A phase-locked loop locking detection method based on an MCU, and an MCU. The MCU comprises an analog to digital converter, a memory unit, and a data processing unit. The analog to digital converter is connected to the memory unit, and t...  
WO/2019/066835A1
A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. Further, the method includes dete...  
WO/2019/067194A1
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data...  
WO/2019/057537A2
There are provided examples of receivers, controller units (e.g., for the receivers) and related methods (e.g. for the receivers). One receiver is provided which comprises: an adjustable sample provider (604) configured to provide sample...  
WO/2019/060124A1
A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal respons...  
WO/2019/060103A1
An integrated circuit is disclosed that implements a delay locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and sec...  

Matches 1 - 50 out of 31,343