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WO/2013/070218 |
Automatic digital sensing and compensation of frequency drift caused by temperature, aging, and/or other effects may be provided by including a compensation capacitor array and a sensing logic. The sensing logic may be configured to dete...
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WO/2013/071274 |
A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning ...
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WO/2013/066161 |
Electronic oscillator circuit, comprising a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a funct...
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WO/2013/066939 |
The presently disclosed subject matter is directed to methods and apparatus enabling production of a stable output from a phase locked loop (PLL) circuit. A crystal controlled oscillator provides a reference signal to the PLL circuit. Te...
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WO/2013/067200 |
A serial bit stream having a given bit per second rate is received and distributed to a plurality of phase shifted samplers. A multi-phase sampling trigger is generated at a rate lower than the given bit per second rate, and each of the ...
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WO/2013/065846 |
In a self-oscillating loop of a self-oscillating class-D amplifier, a variable self-oscillating frequency component for changing the self-oscillating frequency of the self-oscillating loop is provided. The frequency, cycle, or phase of a...
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WO/2013/066160 |
Electronic oscillator circuit, comprising an oscillator, for supplying an oscillation signal with an oscillation frequency dependent on a control signal, a controller for delivering the control signal as a function of a phase difference ...
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WO/2013/063500 |
Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an...
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WO/2013/053087 |
A voltage-controlled oscillator device and a correction method for a voltage-controlled oscillator. The voltage-controlled oscillator device comprises a predistortion module, used for performing predistortion processing on an input volta...
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WO/2013/048478 |
A terminal includes control logic to control a phase-locked loop to output a spread- spectrum clocking signal. The control logic controls the generation of the spread- spectrum clocking signal by adjusting at least one parameter of the p...
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WO/2013/048390 |
Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for...
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WO/2013/037100 |
A radio frequency synthesizer includes a phase lock loop system which is used for outputting a signal with the first frequency and a signal with the second frequency, wherein the signal with the second frequency is a second receiving loc...
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WO/2013/038226 |
A system and method for improving the read distance of a transponder. The transponder comprises an antenna receiving energy from an interrogation signal, a resonant capacitor coupling with the antenna to form a tuned circuit, a charge-pu...
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WO/2013/030330 |
Circuitry for any of a transceiver, a transmitter, and a receiver, has RF circuitry (70), digital circuitry (30, 250, 260), a carrier signal generator (80) to provide a carrier signal to the RF circuitry and a clock generator (90) for ge...
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WO/2013/028181 |
Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.
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WO/2013/028956 |
Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock outp...
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WO/2013/027314 |
The purpose of the present invention is to provide a frequency sweep signal generator, a frequency component analyzer, a wireless device, and a frequency sweep signal generating method, wherein frequency error is small even when a contro...
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WO/2013/022192 |
A phase-locked loop according to one embodiment of the present invention comprises: a phase sensor for generating a phase sensor signal by sensing the phase difference between a reference clock signal and an output clock signal; a charge...
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WO/2013/022679 |
A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a comparator circuit coupled to a reference clock and a phase-corrected output signal. The frequency synthesizer circuit also includes a loop filter...
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WO/2013/022192 |
A phase-locked loop according to one embodiment of the present invention comprises: a phase sensor for generating a phase sensor signal by sensing the phase difference between a reference clock signal and an output clock signal; a charge...
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WO/2013/016530 |
In an apparatus, a control signal is generated in response to a comparison between a reference signal REF and a feedback signal FB. Then, charge is provided to first and second low pass filters (LPFs 202-1, 202-2). The first and second L...
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WO/2013/015977 |
System and circuitry controlling characteristics of periodic signals. In one embodiment adjustment circuitry modifies periodic signal characteristic. A phase detector generates analog input signals indicative of a phase difference betwee...
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WO/2013/015279 |
A compensation device for performing compensation processing to remove image components generated by a quadrature demodulator (5) in relation to a quadrature demodulation signal outputted by the quadrature demodulator (5), which performs...
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WO/2013/016530 |
In an apparatus, a control signal is generated in response to a comparison between a reference signal REF and a feedback signal FB. Then, charge is provided to first and second low pass filters (LPFs 202-1, 202-2). The first and second L...
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WO/2013/011972 |
[Problem] The purpose of the invention is to expand a phase detection range by an arbitrary multiple of the period of a reference clock cycle, and enable an operation cycle to be freely selected when the invention is applied to a DLL cir...
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WO/2013/010901 |
A clock generation circuit comprises an internal clock signal source providing an internal clock signal (CLKJNT) and a synchronization device for synchronization the internal clock signal (CLKJNT) with a reference clock signal (CLK_REF) ...
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WO/2013/008355 |
Provided is a digitally controlled frequency synthesizer that is insusceptible to disturbance/noise and which does not utilize a ∆∑ modulator. The frequency synthesizer for digitally controlling oscillatory frequencies is provided wi...
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WO/2013/004072 |
Provided is a relaxation oscillator, comprising: a first and a second timing capacitors, a first and a second switch devices, a first and a second timing reference generators, a first and a second comparators, a first and a second chargi...
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WO/2013/004015 |
The present invention discloses a rubidium atomic frequency standard and a frequency absolute value correction circuit thereof, which belongs to the field of the atomic frequency standard. The rubidium atomic frequency standard includes ...
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WO/2013/000176 |
A microwave cavity bubble device used for atomic frequency standards comprises an integrated light filtering absorption bubble (1), a microwave cavity (2), a photovoltaic cell (3a,3b), a temperature control component, a magnetic inductio...
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WO/2013/002814 |
Techniques are disclosed relating to oscillator settling time allowance. In one embodiment, an apparatus may include an oscillator and oscillation detection and control circuitry. The oscillation detection and control circuitry may be co...
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WO/2013/002873 |
A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscil...
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WO/2013/002873 |
A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscil...
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WO/2013/000239 |
Provided are a phase-locked loop, a wideband transmitter and a carrier leakage calibration method of the wideband transmitter. The phase-locked loop comprises a phase discriminator, a loop filter and multiple voltage-controlled oscillato...
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WO/2012/177491 |
Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect circuit. The reference multiplier can receive a reference sig...
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WO/2012/178086 |
An oscillatory apparatus and methods of utilizing the same. In one embodiment, the apparatus comprises a force sensor having a proof mass, with one or more sensing electron tunneling electrodes disposed thereon, and a frame comprising on...
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WO/2012/172745 |
A fractional-N frequency synthesizer having a cancellation system for phase discontinuity due to loop gain changes may include a phase detector, a current-changeable charge-pump, a loop filter for providing a tuning signal, a voltage-con...
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WO/2012/173962 |
Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to driv...
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WO/2012/173962 |
Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to driv...
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WO/2012/170775 |
An apparatus for capturing power supply harmonics for use in powering a load, comprising a series resonant circuit coupled between an energy source having a waveform comprising a sinusoidal fundamental frequency and a sinusoidal harmonic...
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WO/2012/169161 |
A variable modulus sigma-delta modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a sigma-delta noise-shaping unit, ...
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WO/2012/167239 |
An apparatus comprising: a first control switch (111) driven by a first bit value; a first weighted switch (141) driven by a first clock signal; a first intermediate node (112) coupled between the first control switch and the first weigh...
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WO/2012/162886 |
An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digi...
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WO/2012/165260 |
Submitted are a signal conversion circuit, a PLL circuit, a delay adjustment circuit, and a phase control circuit, with which miniaturization and reducing quantization noise are possible. In a TSTC (8), low-pass filters (101, 113; Figs. ...
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WO/2012/159647 |
An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency co...
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WO/2012/157234 |
Provided are an accumulator type fractional-N PLL synthesizer that minimizes fractional spurious emissions attributable to periodic switching of the dividing number of a fractional frequency divider and a method for controlling the synth...
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WO/2012/156952 |
A digitally controlled delay device, comprising: at least one delay generating gate devic (Ro) e, whose propagation delay is controlled by limiting operating current by means of a tail transistor (M1, M2 ) that is controlled by its gate ...
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WO/2012/152331 |
A phase locked loop (200, 700, 800) with a phase detector (210, 710, 730) whose output signal varies between maximum and minimum points with the phase difference between input signals. A VCO (220, 720, 740) receives the output signal fro...
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WO/2012/153375 |
Provided is a clock generation circuit, comprising: a counter (306) which counts pulses of an oscillation clock signal which are present within a first period of a reference clock signal; a first time digital conversion apparatus (1501) ...
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WO/2012/151313 |
A dock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference dock to be conditioned and a generated clock. The controlled oscillator i...
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