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Matches 1 - 50 out of 31,258

Document Document Title
WO/2019/094509A1
A signal generator. A voltage controlled oscillator generates a signal that is fed to a comb generator, e.g., a nonlinear transmission line. A tone, from among a comb of tones at the output of the comb generator, is selected by a bandpas...  
WO/2019/091246A1
A method for regulating the frequency division of a phase-locked loop (PLL), which is applied in an embedded system: (S1) acquiring multiple corresponding frequency division points according to a default frequency division value of a PLL...  
WO/2019/092440A1
A circuit portion (100) is provided which comprises a phase expansion portion (111) arranged to receive an oscillating input signal (202) with a first frequency and output a first digital signal (206) having a plurality of parts each hav...  
WO/2019/090127A1
Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (...  
WO/2019/089791A1
A fractional clock generator (104) includes a full quadrant analog interpolator (206). A quadrature clock signal (202) with minimal jitter is provided to the full quadrant analog interpolator (206). The full quadrant analog interpolator ...  
WO/2019/084645A1
The present invention describes a method and a product for chemical equalisation based on the transmission of frequencies that act on the equalisation of chemical elements or substances, consequently adjusting the strengthening or weaken...  
WO/2019/083878A1
Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an...  
WO/2019/077673A1
The present invention addresses the problem of a conventional signal source that the noise of a VCO control voltage increases and the phase noise of an output signal of the signal source degrades. A signal source according to the present...  
WO/2019/079517A1
A computer system for automating the shifting of pixels within a digital video receives a first starting point through a user interface. The first starting point is received through a user selection of a first beginning portion of a vide...  
WO/2019/078993A1
A rail-to-rail sense amplifier includes a PMOS differential pair and an NMOS differential pair (Ml, M2) that are arranged in parallel with regard to a biasing network for driving a class AB output stage (M4, P4). The sense amplifier incl...  
WO/2019/057537A3
There are provided examples of receivers, controller units (e.g., for the receivers) and related methods (e.g. for the receivers). One receiver is provided which comprises: an adjustable sample provider (604) configured to provide sample...  
WO/2019/073841A1
This phase locked loop is provided with: a phase comparison circuit that compares the phase of a first signal and the phase of a second signal corresponding to a clock signal; a loop filter that comprises a resistive element having one e...  
WO/2019/075414A1
Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to ...  
WO/2019/071939A1
Various arrangements for decreasing harmonics of an output digital signal are presented. A programmable current rise-time circuit may be present that controls a rising edge of the output digital signal, wherein the output digital signal ...  
WO/2019/074727A1
An example digital-to-time converter (DTC) (102) includes: a delay chain circuit (301) having a plurality of delay cells (302) coupled in sequence, the delay chain circuit including a first input (Fref) to receive a first clock signal an...  
WO/2019/062224A1
A phase-locked loop locking detection method based on an MCU, and an MCU. The MCU comprises an analog to digital converter, a memory unit, and a data processing unit. The analog to digital converter is connected to the memory unit, and t...  
WO/2019/066835A1
A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. Further, the method includes dete...  
WO/2019/067194A1
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data...  
WO/2019/057537A2
There are provided examples of receivers, controller units (e.g., for the receivers) and related methods (e.g. for the receivers). One receiver is provided which comprises: an adjustable sample provider (604) configured to provide sample...  
WO/2019/060124A1
A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal respons...  
WO/2019/060103A1
An integrated circuit is disclosed that implements a delay locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and sec...  
WO/2019/060143A1
An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third p...  
WO/2018/215991A8
A Phase-locked loop circuit including: a local oscillator (14), configured to generate a timing signal (VLO); a variable- length shift register (19), controlled by the timing signal; and a feedback control circuit (2, 18, 20, 22, 24, 26)...  
WO/2019/060123A1
A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive...  
WO/2019/058419A1
This local oscillator is characterized by being provided with: a frequency generator for outputting a first and second sine wave signal having the same frequency and respectively different phases; a phase detector for outputting a voltag...  
WO/2019/054981A1
Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency incl...  
WO/2019/032159A3
An atomic oscillator device includes an atomic oscillator, a controlled oscillator, a resonance controller, and a cold-atom clock output. The atomic oscillator comprises a two-dimensional optical cooling region (2D OCR) for providing a s...  
WO/2019/049524A1
[Problem] To provide a data reception device by which it is possible to improve communication quality when transmitting/receiving serial data. [Solution] Provided is a data reception device comprising: a signal generation unit that gener...  
WO/2019/048736A1
The invention relates to a frequency reference oscillator device and method of providing a frequency reference signal. The oscillator device comprises a first oscillator comprising a first resonator having first long-term stability and a...  
WO/2019/050867A1
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a fi...  
WO/2019/048737A1
The invention relates to a temperature-compensated microelectromechanical oscillator and a method of fabricating thereof. The oscillator comprises a resonator element comprising highly doped silicon and an actuator for exciting the reson...  
WO/2019/046442A1
For producing a low-power, low-phase noise oscillating signal, using an oscillator (102), a signal is produced having a base frequency component and an Nth harmonic component (112). N is a selected integer, and N > 1. The signal is filte...  
WO/2019/045818A1
A ring oscillator includes: (i) one or more current sources each connected to a supply voltage source; and (ii) oscillation elements connected in series in a ring configuration, each oscillation element including: (a) first and second in...  
WO/2019/037180A1
Provided are a device and method for eliminating electromagnetic interference. The device comprises: a timing control chip (205); and a phase-locked loop module (300) electrically connected to the timing control chip (205). The phase-loc...  
WO/2019/040199A1
An all-digital phase locked loop (ADPLL) includes a digital controlled oscillator (DCO) to generate an output signal of the ADPLL and a time-to-digital converter (TDC) to detect a fractional phase of the DCO. A sampling circuit samples a...  
WO/2019/036338A1
Systems and processes disclosed herein determine the temperature of a crystal, such as a crystal that may be used in a crystal oscillator, using the reference crystal itself. The system can measure the temperature of the crystal without ...  
WO/2019/032085A1
Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise...  
WO/2019/032244A1
Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer...  
WO/2019/025447A1
A phase-locked loop circuit comprises an oscillator (308) having a plurality of operating curves and being suitable for generating an output signal (FOSC). In a calibration state the oscillator(308) is trimmed to an operating curve for u...  
WO/2019/022695A1
A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is config...  
WO/2019/018042A1
A signal source with a wireless frequency reference. A signal loop includes an amplifier and a coupler. The magnitude of the loop gain in the signal loop is substantially equal to 1 at a steady-state amplitude of a signal at a fundamenta...  
WO/2019/017864A1
A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal...  
WO/2019/018102A1
A hybrid PLL is provided that includes an digital integral path and an analog proportional path.  
WO/2019/008879A1
The purpose of the present invention is to obtain an oscillation signal of high spectral purity. An oscillation device 10 pertaining to an embodiment is equipped with: an oscillator 11 wherein the oscillation frequency cannot be controll...  
WO/2019/007337A1
Provided are a method, apparatus and system for compensating for a frequency device, and a computer-readable storage medium. The method comprises the following steps: acquiring a clock signal output by a frequency compensation sensor so ...  
WO/2019/009997A1
Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a firs...  
WO/2019/009978A1
A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the firs...  
WO/2019/009968A1
A quarter-rate clock signal (205 out) is doubled in a frequency doubler (210, 220, 235) to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface (215, 240) to serialize (215) and deserialize (240) data (25...  
WO/2019/010088A1
An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency m...  
WO/2019/008672A1
According to the present invention, a phase frequency comparator (4) compares a reference signal with an output signal of a variable frequency divider (3), and outputs a frequency UP signal and a frequency DOWN signal according to the co...  

Matches 1 - 50 out of 31,258