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WO/2012/061665 |
In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulato...
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WO/2012/061631 |
In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further oper...
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WO/2012/055615 |
The invention relates to a method for transmitting digital data via a line, comprising steps of providing a clock signal and transmitting the digital data synchronously to the clock signal, wherein the clock signal comprises a frequency ...
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WO/2012/054736 |
Charge-based charge pumps are described which include a switchable capacitor configured for connection to a voltage source, a ground, and a charge pump output. A first pair of switches include a first switch configured to connect the swi...
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WO/2012/053983 |
An integrated circuit for a radio frequency (RF) circuit such as a voltage controlled oscillator or an injection locked frequency divider is provided. The integrated circuit architecture includes a primary LC tank circuit comprising a fi...
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WO/2012/051400 |
A Phase-to-Digital Converter (PDC) within a Phase-Locked Loop (PLL) includes a PDC portion and a PDC decoder portion. The PDC portion receives a reference signal FR and a feedback signal FV and generates therefrom a stream of multi-bit d...
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WO/2012/051023 |
A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in ...
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WO/2012/048036 |
A transceiver for multi-standard operation (usable, for example, to communicate signals both of a first wireless communication standard and of a second wireless communication standard) has a mixer that receives a local oscillator signal ...
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WO/2012/041413 |
An integrated circuit device for compensating frequency drift of a controllable oscillator is described. The integrated circuit device includes at least one compensation module including: an input for receiving at least an indication of ...
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WO/2012/041919 |
A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. ...
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WO/2012/041915 |
A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling ...
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WO/2012/038735 |
A tunable delay unit and methods of tuning are provided, comprising a plurality of first delay elements and a plurality of first delay element taps between the first delay elements, wherein the first delay element taps are inputs to a fi...
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WO/2012/035142 |
A method and a system are provided including a clock recovery unit comprising a first phase detector unit; an estimation unit comprising a second phase detector unit; the estimation unit being configured to estimate the gain of the secon...
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WO/2012/035941 |
The disclosed frequency divider circuit is provided with: a variable frequency divider (2) which frequency-divides a periodic signal (s5) with two frequency division ratios and outputs a first frequency-divided signal (c1); a counter cir...
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WO/2012/035800 |
A frequency division circuit according to the present invention comprises: a variable-frequency divider (2) that outputs a first frequency-divided signal (c1) obtained by frequency division of a periodic signal (s5) at two different freq...
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WO/2012/036928 |
A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal....
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WO/2012/031684 |
A circuit arrangement for production of radio-frequency output signals formed by a broadband frequency ramp is described and illustrated, having a reference oscillator (1), a phase detector (2), a loop filter (3), a VC oscillator (4) for...
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WO/2012/032686 |
In a digital PLL frequency synthesizer (101), by switching from a first oscillation signal phase information (Rv[k]) after lock detection to a second oscillation signal phase information (Rv_est[k]) estimated by an estimating unit (20) o...
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WO/2012/030780 |
A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is conne...
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WO/2012/029416 |
A reference signal generation device (10) comprises: a comparison unit (12) which compares a reference signal (r) and a time point signal (y) and outputs a tracking error (e); a control unit (13) which calculates, on the basis of the tra...
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WO/2012/029597 |
The present invention can be applied to high-speed communication of an equalization technique to a duobinary signal, that proactively uses inter-code interference. In such applications, a clock replay circuit that accurately detects cloc...
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WO/2012/025784 |
A method comprises converting an audio frequency domain signal into one or more voltage signals. Then the characteristics of the one or more voltage signals are determined. Afterwards the characteristics of the one or more voltage signal...
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WO/2012/025140 |
A method (10) of measuring the phase of a clock signal, the method comprising: a) receiving a clock signal comprising clock cycles having a clock frequency and a clock period, TClock (12); b) providing a reference clock signal comprising...
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WO/2012/023826 |
The present invention relates to a digital phase locked loop (PLL) in a wireless communication system, and the PLL comprises: a digitally controlled oscillator (DCO) which generates a frequency signal according to an inputted digital tun...
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WO/2012/023826 |
The present invention relates to a digital phase locked loop (PLL) in a wireless communication system, and the PLL comprises: a digitally controlled oscillator (DCO) which generates a frequency signal according to an inputted digital tun...
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WO/2012/021511 |
A frequency divider (200) includes a least significant (LS) stage (220), multiple cascaded divider stages (230-1 to 230-N), and an output stage (210). The LS stage (220) receives an input signal (201), a program bit and a first mode sign...
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WO/2012/020501 |
A high precision digitally controlled oscillator having a small area is provided. A digitally controlled oscillator (DCO) comprises: a ΔΣ modulator (28) which has an order higher than the first order, inputs a digital control signal (D...
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WO/2012/017572 |
A MEMS oscillator is provided with: a feedback oscillation circuit that contains a MEMS resonator and an amplifier; and an automatic gain controller that receives output from the amplifier and controls the amplifier gain on the basis of ...
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WO/2012/013669 |
The invention relates to a system for providing a reference frequency, including a primary quartz oscillator (1) that provides a reference frequency, characterized in that said system comprises: a feedback loop (10) including an auxiliar...
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WO/2012/014060 |
A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input...
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WO/2012/015829 |
In one embodiment, an apparatus includes a jitter generator configured toreceive a r eference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used t...
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WO/2012/013051 |
A phasedetector is disclosed, and the phasedetector includes: a first exclusive-OR gate connected to a trigger and a delay unit, and a second exclusive-OR gate connected to the trigger and a latch, wherein the first exclusive-OR gate is ...
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WO/2012/012042 |
A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitallycontrolled oscillator (DCa) including a sigma- delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a refe...
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WO/2012/009986 |
A phase rotator and a clock and data recovery device are disclosed. Only one clock signal is needed to be input, so that the design difficulty of the phase rotator is reduced. The phase rotator comprises: Metal-Oxide-Semiconductor (MOS) ...
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WO/2012/008197 |
A transmitter-receiver apparatus comprises a plurality of transmitter-receiver blocks including respective phase sync oscillators for generating local oscillation signals used for down-converting respective RF signals received by a plura...
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WO/2012/009160 |
An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signal...
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WO/2012/004116 |
The invention relates to a method for regulating a phase shift between a transmitted signal and a received signal of an electromechanical transducer unit in a tuned circuit to a specified value. The invention is characterized in that the...
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WO/2012/006225 |
Phase detection methods are provided. According to a first embodiment, a signal is sampled in order to obtain an amplitude sample. Then an absolute value of the difference of the amplitude sample minus an average of amplitude samples is ...
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WO/2012/006323 |
A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit i...
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WO/2012/003480 |
A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second porti...
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WO/2012/003480 |
A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second porti...
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WO/2012/001450 |
An integrated circuit device (300) comprises tuning signal circuitry (310) for generating a tuning signal (315) for calibrating a voltage controlled oscillator (VCO) (200). The tuning signal circuitry (310) is arranged to receive a targe...
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WO/2012/003433 |
Methods and apparatus for tuning devices having resonators are described. Phase shifters are included in the circuits and used to shift the phase of the output signal(s) of the resonators. In some implementations, the phase shifters are ...
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WO/2012/001846 |
Disclosed is a reference frequency generating circuit wherein an oscillation circuit (11) increases/reduces the signal levels of oscillation signals (OCSa, OSCb) in a complementary manner, corresponding to transition of the signal levels...
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WO/2011/162923 |
In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the dr...
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WO/2011/161860 |
Disclosed is a frequency synthesizer, comprising a control circuit (20) that generates a digital control signal; and a Digitally Controlled Oscillator (10) wherein an oscillation frequency changes according to the generated digital contr...
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WO/2011/161737 |
A digital phase difference detection device is equipped with: a delay circuit (10) that cumulatively delays first signals and generates signals for each delay amount; a flip-flop group (20) that latches the delay amount signal in synchro...
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WO/2011/162922 |
In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC config...
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WO/2011/156622 |
Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase base...
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WO/2011/153776 |
A phase locked loop (PLL), voltage control device and voltage control method are provided. The PLL comprises a phase detector (402), a filter (404), a voltage control module (406) and an oscillator (408). The voltage control module (406)...
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