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Matches 1 - 50 out of 30,812

Document Document Title
WO/2018/013406A1
A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the fi...  
WO/2018/012083A1
The present invention reduces a leak current while reducing low-frequency noise in an AGC circuit provided with a transistor that shifts to an on state or an off state according to the level of a signal. A switching circuit is provided w...  
WO/2018/012576A1
[Solution] A PLL unit (207-x) generates a sampling clock (Sd-x) on the basis of a word clock (W-x) (x = 0-n), and a PLL unit (207-y) generates a sampling clock (Sd-y) on the basis of a word clock (W-y) (x = 0-n, y≠x). When having the c...  
WO/2018/010732A2
The invention relates to a device (200) for controllably delaying an electrical signal, the device comprising: - a first signal transfer path (207) between a signal input (201) and a signal output (204), the path having -- a first signal...  
WO/2018/013241A1
A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit (100) includes an injection locked oscillator (102), a loop controller (116), and a phase interpolator (108). The inject...  
WO/2018/013327A1
A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage ...  
WO/2018/001526A1
A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and...  
WO/2018/000530A1
A calibration system and method for a voltage-controlled oscillator in a phase-locked loop. The calibration system comprises: a gain regulation unit which is connected to an input end of a voltage-controlled oscillator, and is used for i...  
WO/2018/001667A1
The invention relates to a method for synchronizing an inspection device (10), wherein the inspection device (10) is designed to test at least one first control device and the inspection device (10) comprises at least: one first computin...  
WO/2017/222620A1
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...  
WO/2017/220138A1
A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_1...PLL_N) and a plurality N of phase detectors (DET_1...DET_N). The plurality N of phase detectors and the plurality...  
WO/2017/218085A2
An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at ...  
WO/2017/213798A1
A method includes receiving an optical signal (20) through an optical link (22) and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving p...  
WO/2017/207932A1
The time arbitration circuit (1) includes: a comparator (2) including at least first and second inputs and configured to deliver at least one first piece of information (D) relating to the synchronisation state of the signals (C1, C2) pr...  
WO/2017/206075A1
Disclosed are a clock generator circuit and a clock signal generation method. The method comprises: using a direct current bias circuit in a first clock source, superimposing a first direct current voltage on a first clock signal output ...  
WO/2017/209986A1
An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further...  
WO/2017/204902A1
A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, su...  
WO/2017/198666A1
A MEMS resonator sensor uses a signal generator to generate first and second reference signals of the same frequency, wherein the first reference signal is used to drive a MEMS resonator. A digital controller is used for controlling the ...  
WO/2017/199603A1
A communication system according to the present disclosure is provided with: a transmission apparatus including a phase synchronization unit that is configured to generate a first clock signal and to be able to change a frequency of the ...  
WO/2017/197946A1
Disclosed is a PVTM-based, wide-voltage-range clock stretching circuit. The circuit comprises a PVTM circuit module, a phase clock generation module, a clock synchronization selection module, and a control module. The PVTM circuit module...  
WO/2017/195615A1
The present technology relates to a detection device and a detection method that enable a lock state to be determined more accurately. A first edge detector detects whether an edge of a second clock signal is present in one cycle of a fi...  
WO/2017/195614A1
The present invention relates to an oscillation circuit, an oscillation method, and a PLL circuit, whereby reduced power consumption and suppression of jitter (phase noise) degradation can be achieved at the same time. The oscillation ci...  
WO/2017/189160A1
A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local osci...  
WO/2017/185953A1
Provided is a digital frequency-division phase-locked loop, comprising: a time-to-digital converter, a digital loop filter, a digitally controlled oscillator, a feedback divider, a Sigma-Delta modulator and a correction device. The corre...  
WO/2017/185072A1
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a pluralit...  
WO/2017/184849A1
An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of...  
WO/2017/177864A1
A method and apparatus is described for estimating a local oscillator frequency offset (LOFO) of a received optical signal in a coherent optical receiver. The method includes receiving a signal by the coherent optical receiver; digitally...  
WO/2017/177585A1
Disclosed are a synchronously rotating reference frame phase-locked loop, and a test method and device therefor. The phase-locked loop comprises: a reference transformation module set to, according to a phase angle fed back by a phase-lo...  
WO/2017/177474A1
The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase...  
WO/2017/177064A1
An example clock generator circuit includes a fractional reference generator (202) configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a ...  
WO/2017/174142A1
A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter (1) to provide a digital control word (DFC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback ...  
WO/2017/177062A1
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signa...  
WO/2017/172219A1
A mobile communication device adapted to perform spur relocation for a digital phaselocked loop includes a receiver to determine a first frequency channel of interest and to identify a first frequency command word corresponding to the fi...  
WO/2017/166048A1
Disclosed are a broadband voltage controlled oscillator and a frequency synthesizer. The broadband voltage controlled oscillator comprises: a current source module, a resonance module and a peak value detection module, wherein the curren...  
WO/2017/172282A1
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.  
WO/2017/165107A1
Methods, systems, and devices for wireless communication are described. An internal state of a frequency divider of a local oscillator (LO) may be stored using a storage device in order to facilitate phase flipping of one or more signals...  
WO/2017/160802A1
A system for optical comb carrier envelope offset frequency control includes a mode-locked oscillator. The mode-locked oscillator produces an output beam using an input beam and one or more control signals. The output beam includes a con...  
WO/2017/160731A1
Streaming content using a data streaming device having limited power is described. A data streaming device receives streaming content from a network and provides the streaming content for display on a content display device. Data streami...  
WO/2017/160947A1
The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock ...  
WO/2017/158761A1
A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal outputted from a last-stage one of dual modulus frequency dividers, among a plurality of dual modulus frequency div...  
WO/2017/154126A1
A conventional distortion pulse shifting circuit has a problem that an output timing of a pulse signal cannot be controlled without use of a reset signal. A pulse shifting circuit according to the present invention is provided with: an i...  
WO/2017/154532A1
A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. This pulse shift circuit is provided with: an integrator which integrates an inpu...  
WO/2017/151198A1
The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increas...  
WO/2017/148240A1
A loss-of-lock detection system for a phase-locked loop. An input clock frequency of the phase-locked loop is smaller than an output clock frequency of the phase-locked loop. The system comprises a frequency divider, a trigger, and a cou...  
WO/2017/149978A1
[Problem] To provide a ring oscillator capable of controlling frequency according to the delay amount of a delay element, with a structure for which fine-level frequency setting is possible. [Solution] A reference signal generation devic...  
WO/2017/150241A1
The present technology relates to a phase synchronization circuit and a method for controlling same, with which power consumption is low and phase noise can be improved while suppressing an increase in circuit area. The phase synchroniza...  
WO/2017/146833A2
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/146833A3
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/141258A1
An enhanced jitter tolerant clock and data recovery circuit (CDR) comprises of the blind- oversampling CDR placed in a first order delay locked loop with the data. In the blind oversampling CDR the output clock's position is a function o...  
WO/2017/140651A1
Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, a...  

Matches 1 - 50 out of 30,812