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Matches 1 - 50 out of 31,146

Document Document Title
WO/2019/008879A1
The purpose of the present invention is to obtain an oscillation signal of high spectral purity. An oscillation device 10 pertaining to an embodiment is equipped with: an oscillator 11 wherein the oscillation frequency cannot be controll...  
WO/2019/007337A1
Provided are a method, apparatus and system for compensating for a frequency device, and a computer-readable storage medium. The method comprises the following steps: acquiring a clock signal output by a frequency compensation sensor so ...  
WO/2019/009997A1
Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a firs...  
WO/2019/009978A1
A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the firs...  
WO/2019/009968A1
A quarter-rate clock signal (205 out) is doubled in a frequency doubler (210, 220, 235) to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface (215, 240) to serialize (215) and deserialize (240) data (25...  
WO/2019/010088A1
An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency m...  
WO/2019/008672A1
According to the present invention, a phase frequency comparator (4) compares a reference signal with an output signal of a variable frequency divider (3), and outputs a frequency UP signal and a frequency DOWN signal according to the co...  
WO/2019/003493A1
The clock recovery system (10) is provided with: a sampler part (11) for sampling received data using 2N phase clocks and outputting 2N x M sampling signals; a data selection part (102) for selectively outputting n x M restoration signal...  
WO/2019/004993A1
A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a cl...  
WO/2019/005875A1
A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the div...  
WO/2018/232697A1
A single-phase phase-locked loop based on an all-pass filter and a phase-locking method. The single-phase phase-locked loop comprises: an all-pass filter (102), configured to receive an input grid voltage signal Ui and a frequency signal...  
WO/2018/233675A1
In some examples, a delay apparatus includes a controllable delay line comprising a plurality of delay elements selectively connected in a signal path to vary a delay of a signal passing through the delay line, and a controllable phase s...  
WO/2018/231366A1
A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedb...  
WO/2018/232002A1
Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signal...  
WO/2018/224144A1
A phase controllable Phase Locked Loop, PLL (100) for generating an output signal is disclosed. The PLL comprises a phase frequency detector (200) comprising two latches (210, 220). Each latch comprises a clock input (Clk), a reset input...  
WO/2018/222176A1
Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequ...  
WO/2018/222641A1
Changes in operating conditions, like voltage or temperature, can cause the frequency of an internal clock signal to change and negatively affect device operation. In one embodiment, a method of controlling internal clock frequency of a ...  
WO/2018/217783A1
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal fro...  
WO/2018/216148A1
This PLL frequency synthesizer is provided with: a voltage-controlled oscillator which outputs an oscillation signal having a frequency corresponding to a control voltage value; a phase comparison unit which inputs, as a feedback oscilla...  
WO/2018/215991A1
A Phase-locked loop circuit including: a local oscillator (14), configured to generate a timing signal (VLO); a variable- length shift register (19), controlled by the timing signal; and a feedback control circuit (2, 18, 20, 22, 24, 26)...  
WO/2018/209060A1
A method is presented for determining an offset frequency of a frequency comb. The method includes: generating a beam of light with a waveform that repeats regularly in the time domain and exhibits a frequency comb in the frequency domai...  
WO/2018/198226A1
In conventional signal sources, there has been an issue that due to aliasing caused by sub-sampling, a thermal noise of a comparison signal input to a PFD is degraded, and a phase noise of an output signal from the signal source is degra...  
WO/2018/197646A1
The invention relates to a circuit arrangement for determining an offset between two signal edges of at least one digital signal (A, B) having a signal frequency (f). The circuit arrangement comprises: an adjustment device (110) for adju...  
WO/2018/192654A1
A signal generation device comprises a variable frequency oscillator configured to generate an output signal having an output frequency dependent on an oscillator control signal, and a first frequency division stage (200) configured to g...  
WO/2018/189288A1
An asynchronous state machine (30) for a phase/frequency detector (12) operative in a phase locked loop (10) includes a short pulse suppression circuit (40, 50, 60, 70, 80) operative to suppress output pulses of duration on the order of ...  
WO/2018/186876A1
Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, s...  
WO/2018/187335A1
Some embodiments include apparatuses and methods of operating such apparatuses. One of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an input clock signal and a feedback clock signal, and to ge...  
WO/2018/179920A1
[Problem] To control delay time with high accuracy. [Solution] A delayed locked loop circuit provided with: a first delay circuit that comprises at least one first delay device and at least one second delay device, the first delay device...  
WO/2018/182918A1
Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending ...  
WO/2018/177195A1
A charge pump (1), a charge pump-based processing method and phase-locked loop circuit, and a storage medium. The charge pump comprises a charge pump main circuit (11), a common-mode feedback circuit (12), and a voltage bias circuit (13)...  
WO/2018/175194A2
An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mi...  
WO/2018/171141A1
The present invention relates to a single phase voltage digital phase locking method, and a preset level signal similar to a voltage signal to be measured is constructed. In the control process, according to an angular frequency obtained...  
WO/2018/175194A3
An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mi...  
WO/2018/166130A1
Disclosed are a duty cycle adjustment apparatus and method. The apparatus comprises: a first edge extraction unit (1) for extracting a rising edge of a first clock signal; a lock determination unit (2), with an input end connected to the...  
WO/2018/169561A1
A microfluidic device molded in a single step provides a seamless fluid communication path from fluid input features to microfluidic channels. The device comprises a molded material which is formed around thread for forming high aspect r...  
WO/2018/169653A1
An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and seco...  
WO/2018/164828A1
A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a freq...  
WO/2018/163405A1
An IQ signal source (100) provided with: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the first VCO (1) and the second VCO (2) electrically coupling to thereby output an I signal and a Q signal; a first PLL (10) for comparing...  
WO/2018/162987A1
Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop ("PLL") wherein the holdover PLL is configured to perform a holdover function by receiving a system cl...  
WO/2018/157926A1
A system (200) for phase control of a Phased Locked Loop, PLL, is disclosed. The system comprises said PLL. Said PLL comprises an oscillator (210) configured to generate an output signal; a frequency divider (220) configured to generate ...  
WO/2018/158614A1
A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital conv...  
WO/2018/160578A1
Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a powe...  
WO/2018/149595A1
The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320).The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a c...  
WO/2018/151874A1
Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled...  
WO/2018/145326A1
A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO) (40). A digital data modulation signal is combined with a carrier and input to a feedback divider (52). The data modulation signal i...  
WO/2018/145759A1
A differential electronic circuit (25) comprising a tuning circuit (140, 140-i) connected between a first circuit node (110) and a second circuit node (112) of the electronic circuit (25), is disclosed. The tuning circuit (140, 140-i) co...  
WO/2018/146896A1
A multiband control oscillation unit (23, 223) is provided with a plurality of bands in which frequency is gradually increased or gradually decreased in accordance with a control signal (Vc) apart from each other, and configured such tha...  
WO/2018/145318A1
A Phase-Locked Loop (PLL) has a multi-curve voltage-controlled oscillator (VCO) with a curve-select input that adjusts the capacitance within the VCO and thus the VCO gain. A calibration unit generates a curve-select value to the VCO. Co...  
WO/2018/145612A1
A charge pump circuit and a phase-locked loop, the circuit comprising a start module (10), a bias module (20), a current mirror module (30), a charging and discharging feedback control module (40) and a charging and discharging matching ...  
WO/2018/144207A1
Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit include...  

Matches 1 - 50 out of 31,146