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Patent Searching and Data


Matches 401 - 450 out of 1,613

Document Document Title
JP3603732B2
The objective is to provide a data transfer control device and electronic equipment that implement bit insertion, encoding, decoding, and bit deletion at a slow clock frequency. A bit stuffing circuit and NRZI encoder are provided in a s...  
JP3600233B2  
JP3600234B2  
JP3598702B2  
JP3597142B2
A center phase decision circuit for deciding a center phase of a data signal, in which, in case the data signal is subjected to disturbance in the signal waveform, the signal is corrected for the disturbance to re-establish normal commun...  
JP3596321B2  
JP2004326282A
To provide a digital data arithmetic unit that enables minimum testing terminals and a test on a peripheral circuit as an external interface with the same normal signal transmission path and timing by a simple structure.An arithmetic LSI...  
JP2004320530A
To provide a power supply system device in which the increase of a signal line connecting a control means and a power supply means can be reduced even if the power supply means increases and the quantity of information transmitted/receiv...  
JP2004318670A
To provide an arithmetic unit with a small-scale circuit and capable of high-speed operations.The arithmetic unit is provided with a first parallel/serial conversion circuit which divides first parallel data into a prescribed numbers of ...  
JP3586026B2
PURPOSE: To suppress the power consumption of the flip-flop circuit and to hardly generate malfunction by enlarging an output amplitude. CONSTITUTION: The power consumption is reduced by using a series gate type ECL for the master latch ...  
JP3580242B2
To provide a serial/parallel conversion circuit, a data transfer controller, or the like, which combines serial/parallel conversion function with a buffer function to smooth out clock frequency differences. The serial/parallel conversion...  
JP3577289B2  
JP3570544B2
To provide a received frequency converting device and a frequency band switching method, with which accuracy in switching parallel connected band pass filters can be freely selected by changing the number of bits and positions of frequen...  
JP3565590B2
PURPOSE: To make the characteristic evaluation efficient by realizing the signal generating circuit generating various PN signals and fixed pattern signals while suppressing the increase in the hardware amount thereby reducing the cost o...  
JP3559712B2
A novel latch circuit configuration (100) that substantially reduces inverter-based setup and hold times includes first and second input switches (140, 145) connected to an effective sense amplifier configuration. It is possible for the ...  
JP2004241797A
To provide a multiplexer capable of maintaining high-speed and waveform quality and reducing the power consumption.Level shift circuits 57 to 60, output polarity switching circuits 61 to 64, and output stop circuits 67 to 70 used in comm...  
JP3558118B2
To make it possible to connect between a flat display board and driving devices by simple wiring. In an integrated circuit device for driving a fluorescent display tube where anodes, of which each composes a minimum luminescence unit, ar...  
JP3552932B2  
JP3549756B2
By a shift register, nxd bits of data input Din are converted into parallel signals and latched by a register. A shift register is loaded with the parallel signals latched to the register when a data load signal is at high level and conv...  
JP3548162B2
To accurately search the reference point of an I-Q plane in a simple circuit constitution. A randomizing part 101 equalizes the numbers of 1 and 0 of data. An encoding part 102 encodes the data where the numbers of 1 and 0 are made equal...  
JP2004207894A
To provide a parallel/series conversion circuit capable of realizing a parallel/series conversion using the signal wiring delays and a simple logic circuit.The parallel/series conversion circuit uses the transmission lines as the differe...  
JP2004173168A
To overcome a problem such that in a multiplexer circuit, it becomes difficult to sufficiently secure a band for reducing the voltage and for making a fast operation of the small signal complitude.This multiplexer circuit which synchroni...  
JP2004140752A
To provide a parallel-serial circuit that is constituted by shift register IC's and performs parallel-serial conversion to a switch signal where a shift register IC to which no switch signal is input is left unmounted.When a shift regist...  
JP2004135187A
To provide a parallel/serial conversion circuit having a plurality of parallel/serial converters, which can shorten the time necessary for perform parallel/serial conversion and can suppress expansion of the circuit scale.The parallel/se...  
JP2004134854A
To solve the problem that e.g. EFM modulated signals of less than 3T are detected and decoded into data of normal lengths but the system clock frequency is high to result in a high power consumption with much heating.The decoder decodes ...  
JP3522683B2
To solve the problem of a user having to set an interface scheme among various codec interface schemes associated with digital radio transmission system, including mainly ARIB scheme, DVB-SPI scheme and DVB-ASI scheme above all. A codec ...  
JP2004127449A
To provide a semiconductor storage device which provides the timing of a signal for controlling a read register and a write register with flexibility and has a function for changing data sequences.The device is equipped with a memory cor...  
JP3520052B2
To provide an image signal transmitter that adopts a transmission system suitable for the resolution of an image signal to be transmitted and for the length of a cable so as to transmit the image signal. An image transmission side device...  
JP2004112214A
To provide a serial data receiver capable of outputting correct parallel data even when input serial data are distorted.A parallel conversion section 2 applies parallel conversion to an input serial bit stream subjected to oversampling b...  
JP3516998B2
PURPOSE: To realize forwarding and stripping in a hardware system by converting the data stream of a packet received from an FDDI network into a sixteen bits format, recording it into CAM and decoding it. CONSTITUTION: Destination addres...  
JP3515519B2
To provide a data receiver in which the scale of a serial-to-parallel conversion circuit for transmitting a Viterbi decode signal to a Leed-Solomon decoding circuit is reduced. For instance, in a BS(Broadcasting Satellite) digital broadc...  
JP2004079184A
To rewrite data of one part of a row at high speed in a DRAM.This circuit is provided with a dynamic cell block 11, a sense amplifier sensing the data of the cell block 11, a latch 2 for storing the data, a data transfer gate performing ...  
JP2004069961A
To provide a semiconductor integrated circuit in which a function is provided to convert serial data into parallel data and to store the data and stable operations are realized even though the cycle of writing/reading is made short.The c...  
JP3501732B2
To solve the problems of the conventional parallel serial conversion circuits that they cause clock skew because number of flip-flop circuits and number of HCLK lines increase, when a serial number of the parallel serial conversion circu...  
JP3500028B2
To make it possible to successively output the M.n times fast speed data after demodulation even when (n) times fast data is successively inputted. The time required for plural parallel-input serial-output shift registers 17, 19, 21, 23 ...  
JP2003347941A
To provide an S/P (serial/parallel) conversion circuit with an elastic store that can be operated at a processing speed lower than an input speed of received data. The S/P conversion circuit is provided with: the elastic store 1 for proc...  
JP3471268B2
To provide a logic circuit capable of securing a wide timing margin in control signals even under a high-speed operation and improving operation accuracy. The control signals tA, tB, tC and tD successively rise at each half clock of an e...  
JP2003318741A
To provide a communication system which has a large width for available apparatus characteristics to enhance the flexibility in constituting the apparatus.Upon the receipt of a clock and serial signals from a serial- converting transmitt...  
JP3461486B2
To provide a parallel signal processing unit that can extend the shortest part of a setup margin as a time required, when assembling parallel data into serial data and avoid the power consumption time from being concentrated at a single ...  
JP3456912B2
To prevent malfunction of the title circuit that can easily realize data interface by having only to receive data even when a noise or a hazard signal is superimposed on a clock signal. This circuit 10 is provided with a serial IN/parall...  
JP3454975B2
To obtain a data transmitter which transmits data between two systems with different processing speeds while converting parallel data into serial data. A transmitter is provided with a 1st input latch means 210 that latches N-bit paralle...  
JP2003273749A
To reduce transmission paths while maintaining slow driving (low power consumption) when transmitting a signal.A signal transmitter comprises a parallel/serial conversion part 20 which converts a plurality of first parallel signals A1,.....  
JP2003243991A
To provide a serial-parallel conversion circuit by which the content of output data of a synchronous serial data circuit can be measured in real time without problems even when a conventional slow measuring instrument is employed.A selec...  
JP3441275B2
To lighten the load on a computer and inform a computer of the head position of data which is transferred by reloading all the data together from a reception clock to a clock having a higher frequency than the reception clock. A clock 1 ...  
JP2003218705A
To allow a decoder circuit in a serial data processor circuit to be inspected even if the number of address data increases.The processor circuit comprises: a serial-parallel converter circuit 10 for converting serial data into parallel d...  
JP3431071B2
To reduce CPU processing and to improve system capability by providing a parallel bus, a serial bus and the signal line of an interruption signal which informs CPU of communication termination from a parallel/serial conversion port. The ...  
JP2003198382A
To provide a coding/decoding system for increasing a data transmission rate (throughput) by using a plurality of antennas.The coding/decoding system comprises a supply apparatus for receiving data and for generating N data streams (A), N...  
JP3424230B2
To obtain sure angle data by generating a more detailed control command to secure the responding characteristics of the whole antenna system at the time of driving an antenna to a desired angle. Encoders provided at each driving shaft of...  
JP3420924B2
To provide a multiple conversion method with which the latch timing is not limited by an input frame signal by setting set of delay data to be used for the multiple conversion among those delay data strings which have been prepared in nu...  
JP2003179504A
To provide a high speed and small parallel-serial signal converter.Using respective electric signals 2 inputted in parallel as transmission/cut-off signals for optical switches 81-88, the device is so constituted that the lengths of the ...  

Matches 401 - 450 out of 1,613