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WO/2023/235157A1 |
A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to a...
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WO/2023/226086A1 |
Embodiments of present disclosure provide a data processing circuit and method, a transmitting circuit, and a semiconductor memory. The data processing circuit comprises a preprocessing module and a driving module. The preprocessing modu...
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WO/2023/225574A1 |
A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data...
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WO/2023/165014A1 |
Provided in the present application are a programmable circuit, an integrated circuit and an electronic device. The programmable circuit comprises: a signal conversion module, which converts a parallel signal input by an external circuit...
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WO/2023/136899A1 |
A method including segmenting a multidimensional media stream into a plurality of segments of multidimensional media in a multidimensional space; splitting the segmented multidimensional media stream into a plurality of sub-streams that ...
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WO/2023/130548A1 |
A parallel-to-serial conversion circuit, a parallel-to-serial conversion circuit layout and a memory, relating to the field of semiconductor circuit design. The parallel-to-serial conversion circuit comprises: a plurality of parallel bra...
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WO/2023/130549A1 |
A parallel-to-serial conversion circuit, a parallel-to-serial conversion circuit layout, and a memory, relating to the field of semiconductor circuit design. The parallel-to-serial conversion circuit comprises: a plurality of parallel br...
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WO/2023/027693A1 |
Embodiments of apparatus and method for serializer/deserialization forward flow control are disclosed. In one example, an apparatus for forward flow control can include a first buffer on a first chip. The apparatus can also include a sec...
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WO/2023/003959A1 |
A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content inform...
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WO/2022/240591A1 |
A regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, wherein a gate of...
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WO/2022/181476A1 |
[Problem] To improve transmission efficiency while minimizing transmission latency. [Solution] This communication device is provided with: a communication unit for periodically sending to a communication partner device a plurality of app...
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WO/2022/157853A1 |
Provided is a computing platform wherein high speed operations can be achieved. This photonics/electronics integrated computer comprises a recognition circuit that recognizes an executive instruction including operators and operands outp...
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WO/2022/119909A1 |
Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configu...
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WO/2022/054980A1 |
The present invention relates to an encoding structure and an encoding method carried out by a neural network encoder in a wireless communication system, the method comprising: a first encoding step of encoding input data; a step of carr...
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WO/2022/041973A1 |
Provided are a transmission circuit, an interface circuit and a memory. The transmission circuit comprises: an upper-layer clock pad (101), which is used for transmitting a clock signal; M upper-layer data pads (102), which are used for ...
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WO/2022/010155A1 |
An electronic device according to one embodiment of the present document comprises: a camera module, the camera module comprising a first image sensor and a serializer which is electrically connected to the first image sensor and which c...
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WO/2021/247322A1 |
A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to ...
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WO/2021/224727A1 |
It is provided an improved integrated circuit (10) is provided for driving fast links in radiation-hard applications comprising a PISO device (1) including a transmitting block (2) defining a first basic logic and configured to transmit ...
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WO/2021/178113A1 |
Disclosed embodiments relate, generally, to interfacing serial communication interfaces of a first device with a parallel communication interface of a second device. A first group of two or more serial communication interfaces and an int...
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WO/2021/166906A1 |
The purpose of the present invention is to provide a SerDes interface circuit and a control device which make it possible to use the same SerDes to perform data transfer at different communication rates.　The present invention includes:...
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WO/2021/135478A1 |
A data processing method. The method comprises: acquiring a first coded sequence (S101), and parsing the first coded sequence, wherein when a tolerable error code occurs in the first coded sequence, the first coded sequence can also be c...
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WO/2021/113968A1 |
Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a...
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WO/2021/113113A1 |
A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a se...
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WO/2021/101973A1 |
Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adj...
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WO/2021/067882A1 |
A system includes a power source, a transmitter circuit, a conductor, and a receiver circuit. The transmitter circuit is supplied by the power source and wirelessly supplies the receiver circuit via the conductor. The conductor includes ...
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WO/2020/264330A1 |
A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to gener...
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WO/2020/229265A1 |
The invention relates to a method (700) for determining a time of a flank (200) in a signal (132), wherein the method (700) comprises a step of reading (710) the signal (132) and has a master clock (210) for operating a digital evaluatio...
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WO/2020/068533A1 |
Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to mea...
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WO/2020/047297A1 |
The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may furthe...
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WO/2020/021919A1 |
A multi-lane serializer device 1 is provided with a plurality of serializer circuits 101 to 10N, and a control unit 20. A phase difference detection unit of each of the serializer circuits detects a phase difference between a load signal...
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WO/2019/139592A1 |
Illustrative serializer-deserializer (SerDes) modules and methods employ an indirect backchannel suitable for communicating equalization information and/or other link-related data in the absence of a paired return channel on the receiver...
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WO/2019/003588A1 |
A noise cancel circuit (110) includes: a first parallel/serial conversion circuit (21) for converting input 2N-bit parallel data into serial data; an inversion circuit (20) for inverting one of odd-numbered bits and even-numbered bits of...
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WO/2018/214319A1 |
Disclosed are a SerDes link parameter debugging method and device, and a computer storage medium. The method involves: based on a link clock and a channel characteristic, determining a codec mode; determining a forward error correction m...
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WO/2018/216120A1 |
A wiring aggregation apparatus (1) is provided with one or more subunits (3-1 to 3-3). The subunits (3-1 to 3-3) are provided with: input/output modules (20-1, 20-2) which output, to a control module (10), first serial signals obtained b...
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WO/2018/194115A1 |
Provided are a signal processing circuit for generating an output signal outputted from spatially different output ports on the basis of the bit combination of an input word comprising a plurality of bit signals, a distributed memory in ...
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WO/2018/057259A1 |
An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.
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WO/2018/026562A1 |
A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.
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WO/2017/177103A1 |
Aspects of the invention provide improvements to electromagnetic and other wave-based ranging systems, e.g., RADAR or LIDAR systems, of the type having transmit logic that transmits a pulse based on an applied analog signal. The improvem...
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WO/2017/173608A1 |
Disclosed in the present invention is a device for performing parallel-serial and serial-parallel conversions for serial data transmission , comprising: a parallel-serial conversion unit which receives parallel data, converts the paralle...
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WO/2017/177201A1 |
Aspects of the invention provide improvements to electromagnetic and other wave-based ranging systems, e.g., RADAR or LIDAR systems, of the type having transmit logic that transmits a pulse based on an applied analog signal. The improvem...
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WO/2017/119488A1 |
A serializer device 1 is provided with a first latch unit 11, a second latch unit 12, a conversion unit 13, a frequency division unit 14, a load signal generation unit 15, a phase difference detection unit 16, and a reset indication unit...
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WO/2017/103915A1 |
Digital-to-analog converter for generating analog output signal respective of digital input signal. A first circuit portion of an integrated circuit operable as a lookup table receives digital input having bit-width of "n", and produces ...
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WO/2017/083047A1 |
Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus.In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a hig...
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WO/2017/016081A1 |
Disclosed are a character boundary determination method and apparatus. The method comprises: deserialising acquired serial data to obtain first parallel data with a fixed phase; decoding the first parallel data to obtain decoded second p...
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WO/2016/129718A1 |
According to one preferred embodiment of the present invention, a high-speed serial data reception device comprises: a clock conversion unit for converting a serial clock into parallel clocks; a data conversion unit for converting a seri...
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WO/2016/046883A1 |
A reception circuit provided with: a de-serializer that converts serial data to parallel data in accordance with a processing clock; a phase difference detection unit that detects, on the basis of the parallel data, a phase difference be...
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WO/2016/019054A1 |
Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so...
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WO/2016/018826A1 |
A memory interface architecture uses a serializer/deserializer (SerDes) to connect a memory array on one semiconductor die to a device on another semiconductor die, for example via a fast interposer.
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WO/2015/176244A1 |
Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data strea...
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WO/2015/074067A1 |
A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the fir...
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