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Matches 1 - 50 out of 2,104

Document Document Title
WO/2017/177103A1
Aspects of the invention provide improvements to electromagnetic and other wave-based ranging systems, e.g., RADAR or LIDAR systems, of the type having transmit logic that transmits a pulse based on an applied analog signal. The improvem...  
WO/2017/173608A1
Disclosed in the present invention is a device for performing parallel-serial and serial-parallel conversions for serial data transmission , comprising: a parallel-serial conversion unit which receives parallel data, converts the paralle...  
WO/2017/177201A1
Aspects of the invention provide improvements to electromagnetic and other wave-based ranging systems, e.g., RADAR or LIDAR systems, of the type having transmit logic that transmits a pulse based on an applied analog signal. The improvem...  
WO/2017/119488A1
A serializer device 1 is provided with a first latch unit 11, a second latch unit 12, a conversion unit 13, a frequency division unit 14, a load signal generation unit 15, a phase difference detection unit 16, and a reset indication unit...  
WO/2017/103915A1
Digital-to-analog converter for generating analog output signal respective of digital input signal. A first circuit portion of an integrated circuit operable as a lookup table receives digital input having bit-width of "n", and produces ...  
WO/2017/083047A1
Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus.In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a hig...  
WO/2017/016081A1
Disclosed are a character boundary determination method and apparatus. The method comprises: deserialising acquired serial data to obtain first parallel data with a fixed phase; decoding the first parallel data to obtain decoded second p...  
WO/2016/129718A1
According to one preferred embodiment of the present invention, a high-speed serial data reception device comprises: a clock conversion unit for converting a serial clock into parallel clocks; a data conversion unit for converting a seri...  
WO/2016/046883A1
A reception circuit provided with: a de-serializer that converts serial data to parallel data in accordance with a processing clock; a phase difference detection unit that detects, on the basis of the parallel data, a phase difference be...  
WO/2016/019054A1
Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so...  
WO/2016/018826A1
A memory interface architecture uses a serializer/deserializer (SerDes) to connect a memory array on one semiconductor die to a device on another semiconductor die, for example via a fast interposer.  
WO/2015/176244A1
Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data strea...  
WO/2015/116843A3
Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.  
WO/2015/074067A1
A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the fir...  
WO/2015/065543A1
An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer (210) has a first data path (251) and a data eye path (252). The first data path is coupled to a first data out interface (...  
WO/2014/208552A1
An objective of the present invention is to set an optimal phase with greater precision. A phase adjustment circuit (30) comprises: a phase shift clock generating unit (31) which generates a clock signal of an arbitrarily set phase; a co...  
WO/2014/074300A1
A serializer and de-serializer circuit which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scal...  
WO/2014/055204A1
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder (290), at least one digital frequency mismatch number; decoding, with the at least one decoder (290), the at ...  
WO/2013/139033A1
A configurable media independent interface in an integrated circuit device includes a first plurality of channels and a second plurality of channels, wherein each channel of the first and second pluralities includes a transmit path. The ...  
WO/2013/109263A1
Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a perip...  
WO/2013/061565A1
A serial-to-parallel converter which includes n input latching elements, INL1, INL2,... INLn, configured to sample n successive data of a serial input data stream, respectively; k intermediate latching elements, IL1, IL2,... ILk, configu...  
WO/2013/030298A1
A de-serializer, such as forming part of a SERDES, in which a point in time of receipt, on the serial data path, of receipt of a particular part of a data packet, such as an SOF, is determined from when that part is output on the paralle...  
WO/2012/135458A1
Patterns detected by a low-speed receiver at the output of a high-speed multiplexer are used to determine when multiplexer input lanes are deskewed.  
WO/2012/134652A3
A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consu...  
WO/2012/134652A2
A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consu...  
WO/2012/082572A3
In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase co...  
WO/2012/082572A2
In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase co...  
WO/2012/083279A2
A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter a...  
WO/2012/083279A3
A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter a...  
WO/2012/073809A1
Provided is a method capable of serial transmission of data having varying data values in a constant short period while increase in power consumption is suppressed. A first data sequence conversion circuit (121) and a second data sequenc...  
WO/2012/055615A1
The invention relates to a method for transmitting digital data via a line, comprising steps of providing a clock signal and transmitting the digital data synchronously to the clock signal, wherein the clock signal comprises a frequency ...  
WO/2012/011292A1
In the present disclosures, by means of a control unit (21a), unit data that configures a digital data group is extracted as parallel data having 8-bit units and is output to a buffer (21c). Thereafter, by means of a process of unit data...  
WO/2011/150172A1
A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a s...  
WO/2010/136995A1
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of fr...  
WO/2010/131306A1
A data transmission unit (100) having a parallel/serial conversion function is supplied with a clock by a PLL circuit unit (200). In the PLL circuit unit (200), a first multi-phase clock to be given to a first parallel/serial conversion ...  
WO/2010/097876A1
A transmission unit (210) includes an insertion unit (21) which performs multiple insertion processing for inserting judgment information between each two adjacent line data of a plurality of consecutive line data included in serial imag...  
WO/2010/088016A3
A circuit (301 ) has first portion (302) that receives data at a first rate; a second portion (305) that outputs data at a second rate synchronized to and different from the first rate; a third portion (350) that transfers data from the ...  
WO/2010/083371A1
According to one embodiment, a high speed serializer (100) for multiplexing 2 N data input (D00, D10, D01, D11), N being a positive integer, comprises one less than 2N multiplexing cells (130a, 130b, 130c) arranged in N stages (110,120)....  
WO/2010/067476A1
Provided is a testing apparatus for testing a device to be tested. The testing apparatus is provided with a serializer, which receives a parallel data of N bits (N is an integer of 2 or more), converts the parallel data into M pieces of...  
WO/2010/021164A1
A serializer (15) is equipped with a plurality of input terminals (15a, 15b) into which a plurality of binary signals are input in parallel, and converts the plurality of input binary signals into serial binary signals and transmits the ...  
WO/2009/158541A1
A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit st...  
WO/2009/155874A1
A parallel-serial converter is provided, and the parallel-serial converter comprises a low speed serializer module, a transmission module and a high speed serializer module. A parallel-serial conversion method is also provided, and the p...  
WO/2009/121186A1
A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such...  
WO/2009/121185A1
A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B S...  
WO/2009/025794A2
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing...  
WO/2009/025794A3
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing...  
WO/2009/017386A2
A serializer/deserializer interfaces a microprocessor/controller with I/O devices over a flexible hinging cable. The I/O devices have parallel interfaces as does the controller but the serializer/deserializer reduces the number of signal...  
WO/2009/017386A3
A serializer/deserializer interfaces a microprocessor/controller with I/O devices over a flexible hinging cable. The I/O devices have parallel interfaces as does the controller but the serializer/deserializer reduces the number of signal...  
WO/2009/004263A1
The invention relates to a transition between different sub-band domains for compacting in a single processing operation the application of a first vector X(z), comprising a first number L of components in sub-bands, to a bank of synthes...  
WO2008070978A9
Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, du...  

Matches 1 - 50 out of 2,104