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WO/2012/055615 |
The invention relates to a method for transmitting digital data via a line, comprising steps of providing a clock signal and transmitting the digital data synchronously to the clock signal, wherein the clock signal comprises a frequency ...
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WO/2012/011292 |
In the present disclosures, by means of a control unit (21a), unit data that configures a digital data group is extracted as parallel data having 8-bit units and is output to a buffer (21c). Thereafter, by means of a process of unit data...
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WO/2011/150172 |
A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a s...
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WO/2010/136995 |
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of fr...
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WO/2010/131306 |
A data transmission unit (100) having a parallel/serial conversion function is supplied with a clock by a PLL circuit unit (200). In the PLL circuit unit (200), a first multi-phase clock to be given to a first parallel/serial conversion ...
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WO/2010/097876 |
A transmission unit (210) includes an insertion unit (21) which performs multiple insertion processing for inserting judgment information between each two adjacent line data of a plurality of consecutive line data included in serial imag...
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WO/2010/088016 |
A circuit (301 ) has first portion (302) that receives data at a first rate; a second portion (305) that outputs data at a second rate synchronized to and different from the first rate; a third portion (350) that transfers data from the ...
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WO/2010/083371 |
According to one embodiment, a high speed serializer (100) for multiplexing 2 N data input (D00, D10, D01, D11), N being a positive integer, comprises one less than 2N multiplexing cells (130a, 130b, 130c) arranged in N stages (110,120)....
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WO/2010/067476 |
Provided is a testing apparatus for testing a device to be tested. The testing apparatus is provided with a serializer, which receives a parallel data of N bits (N is an integer of 2 or more), converts the parallel data into M pieces of...
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WO/2010/021164 |
A serializer (15) is equipped with a plurality of input terminals (15a, 15b) into which a plurality of binary signals are input in parallel, and converts the plurality of input binary signals into serial binary signals and transmits the ...
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WO/2009/155874 |
A parallel-serial converter is provided, and the parallel-serial converter comprises a low speed serializer module, a transmission module and a high speed serializer module. A parallel-serial conversion method is also provided, and the p...
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WO/2009/158541 |
A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit st...
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WO/2009/121186 |
A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such...
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WO/2009/121185 |
A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B S...
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WO/2009/025794 |
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing...
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WO/2009/025794 |
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing...
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WO/2009/017386 |
A serializer/deserializer interfaces a microprocessor/controller with I/O devices over a flexible hinging cable. The I/O devices have parallel interfaces as does the controller but the serializer/deserializer reduces the number of signal...
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WO/2009/017386 |
A serializer/deserializer interfaces a microprocessor/controller with I/O devices over a flexible hinging cable. The I/O devices have parallel interfaces as does the controller but the serializer/deserializer reduces the number of signal...
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WO/2009/004263 |
The invention relates to a transition between different sub-band domains for compacting in a single processing operation the application of a first vector X(z), comprising a first number L of components in sub-bands, to a bank of synthes...
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WO/2008/105053 |
A data transmission circuit for converting a parallel data signal into a serial data signal for transmission comprises a clock generation circuit, an output circuit, and a shift register circuit in order to perform the data transmission/...
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WO/2008/104958 |
A data recovery circuit has a delay locked loop circuit (22) for providing clock recovery from an input and generating a multi-phase clock signal (44). This is used to sample input data. A phase locked loop circuit (24) generates an outp...
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WO/2008/104958 |
A data recovery circuit has a delay locked loop circuit (22) for providing clock recovery from an input and generating a multi-phase clock signal (44). This is used to sample input data. A phase locked loop circuit (24) generates an outp...
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WO/2008/070978 |
Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, du...
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WO/2008/067659 |
A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined...
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WO/2008/067665 |
A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and ...
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WO/2008/067652 |
A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and a...
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WO/2008/064466 |
A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is d...
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WO/2008/064028 |
A Serializer/Deserializer (100; 400) apparatus comprises a serializer (100; 400) adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block (110, 120, 420) a...
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WO/2008/064028 |
A Serializer/Deserializer (100; 400) apparatus comprises a serializer (100; 400) adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block (110, 120, 420) a...
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WO/2008/027586 |
A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mo...
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WO/2008/027586 |
A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mo...
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WO/2008/021749 |
A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size...
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WO/2008/008546 |
Universal reconfigurable scan architecture reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask...
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WO/2007/144035 |
An apparatus (2) for parallel/serial conversion of a plurality of evaluation variables which are determined from detected signal variables by in each case one detector (131, 132, 133, 134, 135) comprises a first buffer store (18) for syn...
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WO/2007/109224 |
Embodiments include a serial interface circuit, serial interface method and an apparatus including a serial interface circuit. Embodiments of a serial interface circuit can include a frequency divider implemented by using a counter inste...
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WO/2007/109224 |
Embodiments include a serial interface circuit, serial interface method and an apparatus including a serial interface circuit. Embodiments of a serial interface circuit can include a frequency divider implemented by using a counter inste...
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WO/2007/071574 |
The field of the invention is that of interfaces for transmitting synchronous digital input signals composed of bits sent in series at a transmission frequency equal to a first integer multiple M of a first clock frequency. The interface...
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WO/2007/064785 |
In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter (104a) and a second AC-coupled transmitter. (104b) The first AC-coupled transmitter (104a) includes a first driver having a firs...
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WO/2007/058708 |
In accordance with certain embodiments, an optical network terminal (ONT) is provided that comprises a processor module, a serializer module and an optical transmitter. The processor module may represent an FPGA device, while the seriali...
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WO/2007/044707 |
Methods for communicating data with a circuit associated with a consumable of a printing apparatus, wherein a signal used to communicate data comprises one of at least two states at an object associated with the signal. For example, one ...
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WO/2007/037864 |
A clock circuit for outputting serial data without using a PLL is described. The clock is a VCO designed to start at a frequency that is slightly higher than necessary to preserve the data. The frequency of the clock is measured and if t...
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WO/2007/037132 |
Provided is a parallel-serial conversion circuit, which can set a clock frequency and a data width flexibly. The parallel-serial conversion circuit (100) converts parallel data of a clock frequency (f) and (m x n) (m and n are natural nu...
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WO/2007/033305 |
A system and method of transmitting and receiving bit serial information is disclosed. In a differential embodiment, serial bits are transmitted by a pair of line-matched differential drivers that are ac coupled to a two-conductor transm...
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WO/2007/027833 |
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply nois...
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WO/2007/027833 |
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply nois...
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WO/2006/085323 |
An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a ...
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WO/2006/081096 |
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs...
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WO/2006/081096 |
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs...
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WO/2006/074870 |
The invention relates to a controller for generation of control signals (evload_o, odload_o, st_chgclk_o, clk_o, clk_or_fiford_i), synchronous with a continuously supplied clock signal (clk_hr_i) for a device (1) for control synchronousl...
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WO/2006/058052 |
A double data rate serial encoder (Fig.5) is provided. The serial encoder comprises a mux (508) having a plurality of inputs (510), a plurality of latches (502) coupled to the inputs of the mux, an enabler (504) to enable the latches to ...
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