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Patent Searching and Data


Matches 551 - 600 out of 38,727

Document Document Title
WO/2014/181573A1
A first clock generation circuit (21) generates a first clock that rises with a delay of αT (0.5<α<1.0) from the transition point of each data in a Manchester-coded received signal having a cycle of T. A second clock generation circuit...  
WO/2014/179875A1
A capability is provided for statelessly load balancing Transmission Control Protocol (TCP) connections across a set of servers. A load balancer receives a TCP SYN packet from a client, selects a server for a TCP connection for the clien...  
WO/2014/180347A1
The present invention provides a synchronization method, an intermediate node, and a slave node of a communications network system. An intermediate node obtains, according to a local clock frequency of the intermediate node and an obtain...  
WO/2014/180404A1
A clock recovery method and device. The present invention relates to the field of communications, and solves the problem of the sampling clock of a transmitter and of a receiver not being synchronized. The method comprises: calculating, ...  
WO/2014/176789A1
The present invention relates to the field of communications. Disclosed in an embodiment of the present invention are a clock recovery method, device and system. The method of a central office utilizing an orthogonal sequence to modulate...  
WO/2014/178314A1
A transmission apparatus (1) transmits data signals to a reception apparatus (2) using a first clock generated on the basis of given clock signals, and switches an operating band of a PLL unit (112) to an operating band that includes a f...  
WO/2014/178275A1
In order to reduce the power consumed by a wireless carrier wave, this transmission device is equipped with: a data reception unit that receives, from a network, continuous data which includes real data and null data; a packetization uni...  
WO/2014/173267A1
Provided are a timestamp generating method, device and system, the method comprising: receiving via a data packet processing unit a data packet transmitted by a physical layer (PHY) transceiving unit or by a high layer, and identifying w...  
WO/2014/173240A1
The embodiments of the present invention provide a method, device and system for processing configuration information about a reference signal. A base station can notify a UE of reduced information about a reference signal through a sync...  
WO/2014/171242A1
A communication system (50) in which a plurality of base stations (10 (101, 102,...)) perform transmission on the same frequency at the same timing, wherein a control station (40) serving as a base station control device which gives oper...  
WO/2014/171090A1
Provided is a novel frequency synchronization apparatus that achieves the establishment of frequency synchronization using an IP network. A frequency synchronization apparatus (10), which synchronizes the clock frequencies between a mast...  
WO/2014/170181A1
A communication system comprises a host communication circuit (HCC) and a client communication circuit (PCC), which are connected to each other by means of a single signal wire (DEN). The host communication circuit (HCC) generates a volt...  
WO/2014/170419A1
A coded light receiver comprising a sensor for receiving coded light, a filter, and a timing and data recovery module. The coded light comprises a signal whereby data and timing are modulated into the light according to a self-clocking c...  
WO/2014/165169A9
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is conti...  
WO/2014/165169A3
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is conti...  
WO/2014/161213A1
Disclosed are a clock synchronization method and apparatus in a seamless redundant network, so as to solve the problem in the prior art that precision of synchronization between a primary node clock and a secondary node clock is low. The...  
WO/2014/165215A1
Methods and systems to explicitly realign packets are described. The system includes a first communications device that receives a first stream of bytes comprising a first packet and generates realignment information for the first packet...  
WO/2014/155927A1
A first generation unit (242) and a second generation unit (212) each generate a plurality of packets to be arranged between acquired frame pulses. The second generation unit (212) incorporates, into each of TOT packets that are some of ...  
WO/2014/159083A1
Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. A wireless device may include an LO generator and a phase detector. The LO generator generates an LO signal used for frequency c...  
WO/2014/153656A1
The present disclosure provides a system which collects data from a set of sensors installed on underground vehicles which is then transferred to a remote data collection node through multiple communication protocol/channels according to...  
WO/2014/146708A1
The present invention relates to a timing recovery apparatus, comprising: a grouper for grouping digital signal values of a digital signal to obtain groups of values, each group of values comprising a first digital value and a second dig...  
WO/2014/146274A1
The embodiments disclose a method and apparatus for implementing the clock holdover in the communication system. The apparatus receives an external source clock and outputs an output clock, and comprises a first phase-locked circuit and ...  
WO/2014/148730A1
A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the esti...  
WO/2014/146554A1
Disclosed in an embodiment of the present invention are a method and system for packet synchronization on a process layer network of an intelligent substation, the method comprising: recording the transmission delay on a network transmis...  
WO/2014/153472A1
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire opendrain link by determining a transition in a signal received from the multi-wire...  
WO/2014/146267A1
Disclosed are a time compensation apparatus and method for a master device, a time compensation apparatus and method for a slave device, and a time compensation system. The time compensation apparatus for the master device comprises: a c...  
WO/2014/141651A1
A synchronous measurement system includes a controller and a sensor unit connected to the controller. The controller transmits a plurality of synchronization commands to the sensor unit at every predetermined interval. The sensor unit tr...  
WO/2014/134965A1
Provided in an embodiment of the present disclosure are a multi-party video sharing method and device, the method comprising: initiating a multi-party video sharing request to a called terminal; determining the time difference between th...  
WO/2014/138640A1
A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol...  
WO/2014/137346A1
A distributed antenna system includes a central processing facility and a set of spatially-distributed antennas that are directly connected to the central processing facility. The spatially-distributed antennas are directly connected to ...  
WO/2014/137347A1
According to an example, a distributed antenna system includes a central processing apparatus and a plurality of antenna apparatuses connected to the central processing apparatus via Ethernet cables through an Ethernet switch. The plural...  
WO/2014/136397A1
The purpose of the present invention is to provide a communication device and a method of determining communication method making it possible to receive frames of different communication methods without configuring a synchronization sign...  
WO/2014/138334A1
A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is...  
WO/2014/138581A1
A serial transmission peripheral device for transmitting serial transmission data with a variable data length includes a pulse forming unit; and a register programmable to set a desired transmission length. The peripheral device is opera...  
WO/2014/132351A1
A fixed delay time storage unit (270) stores a predetermined fixed delay time (271) as an amount of time equal to or greater than the time required for transmission of a typical frame. A frame reception unit (210) receives a synchronizat...  
WO/2014/130303A1
Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential dat...  
WO/2014/127407A1
A method for estimating a time offset of a transmitted signal which comprises pilot symbols and data symbols, the method comprising: receiving the transmitted signal to produce a received signal; and processing an optimising function of ...  
WO/2014/130794A1
A distributed antenna system (DAS) includes: first base station network interface unit that receives first downlink signals from first external device and converts them into first downlink data stream; second base station network interfa...  
WO/2014/127514A1
A method of data-aided timing recovery for Ethernet systems is disclosed. A first device negotiates a pseudorandom number sequence with a second device and receives a data signal from the second device. The first device samples the recei...  
WO/2014/125293A3
A communications system (10) is disclosed comprising a transmitter (20) and a receiver (30). The transmitter (20) is configured to transmit a data stream at close to the Nyquist rate. The receiver (30) is configured to sample a received ...  
WO/2014/126237A1
Provided is a synchronous serial interface circuit that is capable of achieving synchronous serial interface (SSI) communications on multiple channels without increasing a data updating interval per one channel while using a small number...  
WO/2014/125293A2
A communications system (10) is disclosed comprising a transmitter (20) and a receiver (30). The transmitter (20) is configured to transmit a data stream at close to the Nyquist rate. The receiver (30) is configured to sample a received ...  
WO/2014/120685A1
Systems and methods for detecting a synchronization code word embedded in a plurality of frames of a signal are described. In one example embodiment, the synchronization code word contains "s" bits, embedded one bit per frame in "s" fram...  
WO/2014/121057A1
A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N ...  
WO/2014/115608A1
The present technology pertains to a signal processing device, a signal processing method, and a program that allow a serial clock and a parallel clock corresponding to an average frequency close to a TS bitrate for a higher resolution t...  
WO/2014/113994A1
A method of initializing a receiver is performed during an initialization mode. Timing offset values for a timing recovery circuit are repeatedly selected. For each selected timing offset value, timing recovery is performed using the tim...  
WO/2014/113400A1
Systems and methods for synchronizing a power line communication system (100) including a power line (104) and one or more devices (102A) communicatively coupled (112A) to the power line. A mains frequency (106) of the power line is esti...  
WO/2014/109255A1
The present technology relates to a data processing device, a data processing method, and a program, whereby it is possible to derive a time error with high precision. A time difference of interest which draws attention among a series of...  
WO/2014/107717A1
The notion of a "PTP aware" path is one current proposed approach to reduce asymmetry effects. In a fully PTP aware path there is the notion of on-path support mechanisms such as boundary clocks and transparent clocks at every switching ...  
WO/2014/107580A1
In one example, a client device for receiving information for streaming of media data includes a clock, and one or more processors configured to receive a media presentation description (MPD) for media content, wherein the MPD includes d...  

Matches 551 - 600 out of 38,727