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Patent Searching and Data


Matches 651 - 700 out of 38,599

Document Document Title
WO/2013/174025A1
Provided are a transparent clock passive port election method and device based on the PTP protocol. In the method, by extracting the TLV field of a received announce message, a first port of a network device acquires the clock identifica...  
WO/2013/172748A1
There is disclosed a method for estimating a frequency offset between a mobile communication terminal and a network node. The method is based on processing, by means of a matched filter, a preamble sequence for random access received on ...  
WO/2013/173809A1
Systems and methods are described for enhancing the channel spatial diversity in a multiple antenna system (MAS) with multi-user (MU) transmissions ("MU-MAS"), by exploiting channel selectivity indicators. The proposed methods are: i) an...  
WO/2013/170359A1
In a computer-implemented method of adjusting a local clock at a receiver in a packet network, the local clock is generated by a phase locked loop locked to a master clock with the aid of time-stamped timing packets arriving over the net...  
WO/2013/170736A1
Disclosed are a packet network synchronization method, apparatus and system. The method comprises: a synchronous device mapping a synchronization status of a frequency layer to a synchronization status message of a time layer, and inform...  
WO/2013/172678A1
A method and an apparatus for performing synchronization by a first device in a Device-to-Device (D2D) network are provided. The method includes detecting a synchronization signal from at least one second device during one period, determ...  
WO/2013/170261A1
Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functio...  
WO/2013/167079A3
Disclosed is a method for synchronizing time in a short distance, comprising: a receiver receiving time service machine local time broadcast by more than one time service machine, and selecting time broadcast by one time service machine ...  
WO/2013/163793A1
A method and apparatus for enabling automatic time and frequency synchronization over an asynchronous network (e.g., an Ethernet network) provide increased clock synchronization accuracy, reduce clock synchronization traffic, and decreas...  
WO/2013/159223A1
Various exemplary embodiments relate to a method and related network node including one or more of the following: displaying, by the network management system, a first representation of a synchronization topology, wherein the synchroniza...  
WO/2013/159222A1
Various exemplary embodiments relate to a method and related network node including one or more of the following: displaying, by the network management system, a first representation of a synchronization topology, wherein the synchroniza...  
WO/2013/161110A1
The objective of the present invention is to achieve a communication system, communication device, and time information correction method which, in a communication system in which a plurality of communication devices are connected, is ca...  
WO/2013/159486A1
Disclosed is a PTP clock source switching method, which comprises: when a PTP clock source is selected, sending a first bidirectional forwarding detection (BFD) negotiation message to a master clock device, the first BFD negotiation mess...  
WO/2013/157677A1
The present invention relates to a communication speed correcting device for stable communication in a serial communication system and provides a communication speed correcting device that may easily implement high-precision, stable, hig...  
WO/2013/152700A1
Disclosed are a clock source selection method and device for a microwave network element. The method comprises: through clock input ports, a current microwave network element receiving synchronization state information which is transmitt...  
WO/2013/154025A1
The present invention pertains to an information processing device and method, and program, wherein it is possible to easily synchronize videos when transferring image data. This information processing device is provided with: a synchron...  
WO/2013/153057A1
A process data transmitter transmits current process data at defined recurring intervals of time in the form of a serial transmission data stream (66) having a multiplicity of data symbols (68) at a defined symbol rate. A process data re...  
WO/2013/149847A1
The present document relates to optical transmission systems. In particular, the present document relates to high efficiency wavelength division multiplexing (WDM) optical communication systems. An optical transmitter (210) adapted to tr...  
WO/2013/143385A1
A slave device obtains a downlink delay time by sending a first test signal via a downlink optical waveguide to a master device and recording a first transmission time, receiving the first test signal looped back by the master device via...  
WO/2013/147514A1
Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plura...  
WO/2013/143959A1
Method of detection and synchronization for a multistation wireless communication system (WiFi) implementing a layer, termed the MAC layer ("Medium Access Control layer"), provided for implementing a multiple access protocol and a physic...  
WO/2013/139662A1
The invention relates to the time synchronization of (logical) clocks in a vehicle. In particular, the invention relates to the time synchronization of clocks in nodes of different bus systems of a vehicle. A gateway (101) for a vehicle ...  
WO/2013/137863A1
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise ...  
WO/2013/136298A3
Systems and techniques for joint transmission cooperative multi-point operation are described. A set of n channel state information reference signal resources is configured, which are to be measured by a user device. The set of n channel...  
WO/2013/132580A1
A multi-rate recovery device includes an M[Hz]√óN-phase sampling circuit (1) that oversamples input data, a phase group selection circuit (2) that outputs phase group data from N-phase sampling data, an N-phase data selection circuit (6)...  
WO/2013/132716A1
This invention is provided with: a M[Hz] x N phase sampling circuit (1) for oversampling input data; a topological group selection circuit (2) for outputting topological group data from N-phase sampling data; an N-phase data selection ci...  
WO/2013/132667A1
The objective of the invention is to provide a synchronization data processing circuit, which achieves a stable circuit operation, and a mobile terminal apparatus. A synchronization data processing circuit comprises: first circuits each ...  
WO/2013/128112A1
The invention relates to a periodic communication method between at least one first system (2) and at least one second system (3) by means of a full-duplex synchronous serial link (4), wherein, during a communication period, data are exc...  
WO/2013/130042A1
Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that configured to generate an estimated phase ...  
WO/2013/129672A1
Provided are nodes which configure an ad hoc network, and in which the local time for each node is set on the basis of time information propagated in sequence from a time synchronization source. Each node is provided with a time differen...  
WO/2013/130460A1
Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of modulation and coding schemes (MCS) available to an orthogonal frequency division mu...  
WO/2013/124929A1
Provided is a timing adjustment circuit for automatically adjusting the phase of a clock signal that determines the timing of a switching in a flip-flop. In a timing adjustment circuit (100), a branch unit (15) branches an input data sig...  
WO/2013/126440A2
Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock ...  
WO/2013/126440A3
Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock ...  
WO/2013/124136A1
This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of ...  
WO/2013/121764A1
Provided is a receiver circuit which without having to be provided with a PLL circuit and the like is capable of high speed signal reception while taking mounting factors into account. A first receiver circuit (2301) which acquires input...  
WO/2013/122562A1
Methods and systems of operating an audio receiver may include a reference module configured to determine an input number of clocks per number of frames for an audio signal based on a reference clock and a specified number of frames. The...  
WO/2013/123427A1
Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data strea...  
WO/2013/117415A1
The invention relates to a reception arrangement (3) for a control device in a vehicle, comprising a voltage generator (30) for generating a synchronisation pulse, said synchronisation pulse being generated with a predetermined shape and...  
WO/2013/117143A1
A clock synchronization method comprises: a synchronization device selecting a clock source, inspecting the current status of a phase-locked loop, and determining a clock quality level to be sent to a downstream device according to the s...  
WO/2013/115016A1
The present technology pertains to a synchronization processing device, a synchronization processing method, and a program, which make it possible to achieve frequency synchronization in a shorter period of time. A jitter amount calculat...  
WO/2013/113292A1
An apparatus for synchronizing a plurality of digital subscriber line access multiplexers (DSLAMs) comprising a reference clock configured to generate a reference clock signal, and an interface configured to transmit the reference clock ...  
WO/2013/113167A1
A signal processing method and apparatus in a microwave communication system. The method comprises: equalizing each source signal using an equalizer, to obtain equalized signal corresponding to each input signal; performing a phase estim...  
WO/2013/114853A1
Provided is a peak detection circuit which handles a plurality of types of peak detection methods for a predetermined processing result. The peak detection circuit detects a maximal value in an input processing result and selects the pro...  
WO/2013/113570A1
The invention relates to a reception arrangement (3) for a control device in a vehicle with a voltage generator (30) for generating a synchronisation pulse, comprising a first voltage source (3.1), a current source (3.5) and a current si...  
WO/2013/110336A1
The invention relates to a clock recovery device and method for establishing synchronization with a received communication signal. The invention is based on a two-state clock recovery mechanism. When in a first state, whenever the receiv...  
WO/2013/112763A1
A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include...  
WO/2013/110772A1
A clock recovery device arranged to receive a communications signal,a first and a second clock input signal,a control signal and a data signal. The clock recovery device comprises means for sampling the received communications signal bas...  
WO/2013/112701A1
The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. A clock-data recovery (CDR) circuit (100) for out-of-lock (including false lock) detection includes a phase/frequency detector (PFD) (1...  
WO/2013/108350A1
A delay circuit (100) is provided with: a first control circuit (130), which outputs first control signals (E101-E105); a second control circuit (140), which outputs second control signals (E111-E115); a plurality of buffer circuits (101...  

Matches 651 - 700 out of 38,599