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Patent Searching and Data


Matches 651 - 700 out of 38,665

Document Document Title
WO/2013/139662A1
The invention relates to the time synchronization of (logical) clocks in a vehicle. In particular, the invention relates to the time synchronization of clocks in nodes of different bus systems of a vehicle. A gateway (101) for a vehicle ...  
WO/2013/137863A1
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise ...  
WO/2013/136298A3
Systems and techniques for joint transmission cooperative multi-point operation are described. A set of n channel state information reference signal resources is configured, which are to be measured by a user device. The set of n channel...  
WO/2013/132580A1
A multi-rate recovery device includes an M[Hz]√óN-phase sampling circuit (1) that oversamples input data, a phase group selection circuit (2) that outputs phase group data from N-phase sampling data, an N-phase data selection circuit (6)...  
WO/2013/132716A1
This invention is provided with: a M[Hz] x N phase sampling circuit (1) for oversampling input data; a topological group selection circuit (2) for outputting topological group data from N-phase sampling data; an N-phase data selection ci...  
WO/2013/132667A1
The objective of the invention is to provide a synchronization data processing circuit, which achieves a stable circuit operation, and a mobile terminal apparatus. A synchronization data processing circuit comprises: first circuits each ...  
WO/2013/128112A1
The invention relates to a periodic communication method between at least one first system (2) and at least one second system (3) by means of a full-duplex synchronous serial link (4), wherein, during a communication period, data are exc...  
WO/2013/130042A1
Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that configured to generate an estimated phase ...  
WO/2013/129672A1
Provided are nodes which configure an ad hoc network, and in which the local time for each node is set on the basis of time information propagated in sequence from a time synchronization source. Each node is provided with a time differen...  
WO/2013/130460A1
Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of modulation and coding schemes (MCS) available to an orthogonal frequency division mu...  
WO/2013/124929A1
Provided is a timing adjustment circuit for automatically adjusting the phase of a clock signal that determines the timing of a switching in a flip-flop. In a timing adjustment circuit (100), a branch unit (15) branches an input data sig...  
WO/2013/126440A2
Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock ...  
WO/2013/126440A3
Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock ...  
WO/2013/124136A1
This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of ...  
WO/2013/121764A1
Provided is a receiver circuit which without having to be provided with a PLL circuit and the like is capable of high speed signal reception while taking mounting factors into account. A first receiver circuit (2301) which acquires input...  
WO/2013/122562A1
Methods and systems of operating an audio receiver may include a reference module configured to determine an input number of clocks per number of frames for an audio signal based on a reference clock and a specified number of frames. The...  
WO/2013/123427A1
Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data strea...  
WO/2013/117415A1
The invention relates to a reception arrangement (3) for a control device in a vehicle, comprising a voltage generator (30) for generating a synchronisation pulse, said synchronisation pulse being generated with a predetermined shape and...  
WO/2013/117143A1
A clock synchronization method comprises: a synchronization device selecting a clock source, inspecting the current status of a phase-locked loop, and determining a clock quality level to be sent to a downstream device according to the s...  
WO/2013/115016A1
The present technology pertains to a synchronization processing device, a synchronization processing method, and a program, which make it possible to achieve frequency synchronization in a shorter period of time. A jitter amount calculat...  
WO/2013/113292A1
An apparatus for synchronizing a plurality of digital subscriber line access multiplexers (DSLAMs) comprising a reference clock configured to generate a reference clock signal, and an interface configured to transmit the reference clock ...  
WO/2013/113167A1
A signal processing method and apparatus in a microwave communication system. The method comprises: equalizing each source signal using an equalizer, to obtain equalized signal corresponding to each input signal; performing a phase estim...  
WO/2013/114853A1
Provided is a peak detection circuit which handles a plurality of types of peak detection methods for a predetermined processing result. The peak detection circuit detects a maximal value in an input processing result and selects the pro...  
WO/2013/113570A1
The invention relates to a reception arrangement (3) for a control device in a vehicle with a voltage generator (30) for generating a synchronisation pulse, comprising a first voltage source (3.1), a current source (3.5) and a current si...  
WO/2013/110336A1
The invention relates to a clock recovery device and method for establishing synchronization with a received communication signal. The invention is based on a two-state clock recovery mechanism. When in a first state, whenever the receiv...  
WO/2013/112763A1
A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include...  
WO/2013/110772A1
A clock recovery device arranged to receive a communications signal,a first and a second clock input signal,a control signal and a data signal. The clock recovery device comprises means for sampling the received communications signal bas...  
WO/2013/112701A1
The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. A clock-data recovery (CDR) circuit (100) for out-of-lock (including false lock) detection includes a phase/frequency detector (PFD) (1...  
WO/2013/108350A1
A delay circuit (100) is provided with: a first control circuit (130), which outputs first control signals (E101-E105); a second control circuit (140), which outputs second control signals (E111-E115); a plurality of buffer circuits (101...  
WO/2013/102730A1
The invention comprises a method for transmission of an acknowledgement frame (AF1) by a receiving entity (ER1), characterised in that the method comprises, following reception of a data frame (DF1) transmitted by a transmitting entity (...  
WO/2013/100019A1
The objective of the present invention is, in a time synchronization system using a plurality of networks, to provide a time synchronization system for executing suitable time correction even immediately after switching of a network. The...  
WO/2013/101413A2
A communication method includes the steps of, at a first system, communicating with a second system for the establishment of a mutual clock and, at the first system, performing a first set of operations based on the mutual clock and perf...  
WO/2013/099122A1
An apparatus includes a receiver (21), a delay value receiver (25), a time stamp calculation unit (29), and a transmitter (25). The receiver (21) is configured to receive a content signal. The delay value receiver (25) is configured to r...  
WO/2013/098369A1
A received POLMUX signal is rotated by fixed rotation parameters (Rot0, Rot1, Rot2) and the rotated POLMUX signal with optimal signal performance is selected and phase information is derived from both polarities. A pre-filter improves th...  
WO/2013/096295A1
Method and apparatus for transmitting combined power and data. In one embodiment, the apparatus comprises an isolation barrier; a drive controller for generating a first waveform comprising a plurality of data signals for transmitting di...  
WO/2013/094671A1
A network node for transferring packets, wherein the network node is provided with: a port through which the transferred packet is inputted and outputted; a buffer memory for temporarily storing the inputted packet; a search engine for d...  
WO/2013/092101A1
A synchronous data transmission device for transmitting data (D, D') between two communications partners (K1, K2), one functioning as a transmitter and one as a receiver, is described. The device is capable of transmitting information re...  
WO/2013/086959A1
Disclosed are a method, device, and system for line asymmetry compensation. The method comprises: by establishing an outer ring synchronization session and an inner ring synchronization session, slave clock devices acquiring transmission...  
WO/2013/086833A1
Disclosed are a clock time synchronization source configuration method and device. The method includes: determining a whole network clock global parameter and a time global parameter according to the network planning of a clock time netw...  
WO/2013/090434A1
One embodiment includes an adaptive sample quantization system. The adaptive sample quantization system includes an antenna to receive a radio frequency (RF) signal having data encoded therein, and analog antenna electronics configured t...  
WO/2013/083190A1
The invention relates to a method (100) for recovering clock information from a received optical signal, the received optical signal having a first (x) and a second (y) principal state of polarization. The method comprises modifying (101...  
WO/2013/082812A1
Disclosed is a method for determining a master clock device, comprising receiving a first message sent by a first clock device, the first message comprising first clock level information, and the first clock level information being deter...  
WO/2013/078926A1
A method and communication system for obtaining time deviation between a primary device and a secondary device in case of fiber optic asymmetry, the method comprising: the primary device transmits a first packet to the secondary device v...  
WO/2013/079365A1
The invention relates to a method for synchronizing clocks (1, 2) in nodes of a vehicle network of a motor vehicle, wherein the nodes communicate with one another by means of a communication protocol that is not synchronized per se, and ...  
WO/2013/078100A1
A slave communication device may transmit a packet to the master communication device, with the packet including a transmission time field and a correction field. The transmission time field may contain a value indicative of an approxima...  
WO/2013/076796A1
This frequency switching circuit includes: a first counting circuit which counts the number of pulses of a first clock signal in a predetermined period in order to generate a first count value; a second counting circuit which counts the ...  
WO/2013/074159A1
A system and method for a radio controlled clock receiver adapted to extract timing and time information from a phase modulated signal. The official time signal is broadcast from a central location using a modulation scheme that adds pha...  
WO/2013/071807A1
A method, a system and an apparatus for implementing hybrid networking of multiple clock synchronization technologies. A master clock and one or more slave clocks are set for a synchronization device serving as both a clock synchronizati...  
WO/2013/071506A1
A method, apparatus and computer program product are provided for generating Reference Signals utilized in downlink tracking of an unlicensed band. A method and apparatus may determine whether carriers of an unlicensed band secondary com...  
WO/2013/075009A3
A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase s...  

Matches 651 - 700 out of 38,665