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7468549 |
The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within t...
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7468525 |
In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, ...
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7467360 |
An LSI design support apparatus includes a data acquisition section and an equal processing section. The data acquisition section acquires first position data concerning positions of a plurality of first electrodes provided along a side ...
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7466157 |
An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device ...
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7456449 |
A semiconductor apparatus has a substrate to which is attached a thin semiconductor film including at least one semiconductor device. An interconnecting line links the semiconductor film with electrical circuitry on the substrate. The in...
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7456033 |
The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where...
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7455939 |
A method of making a process monitor grating pattern for use in a lithographic imaging system comprises determining minimum resolvable pitch of a plurality of spaced, adjacent line elements, and selecting a process monitor grating period...
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7453272 |
A method is disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon...
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7449909 |
A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies ...
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7449716 |
A bump structure on a substrate including at least one first electrode, at least one first bump, at least one second bump is provided. The first electrode is disposed on the substrate. The first bump is disposed on the first electrode. T...
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7439586 |
A base thin film transistor (TFT) substrate includes a substrate, array areas on the substrate; at least one dummy area on the substrate and between the array areas; an insulating film on the substrate; at least one aperture through the ...
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7439538 |
A test structure in accordance with the present invention allows for testing of both V bd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of parallel polysilicon gate structures overlyi...
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7439122 |
A p impurity region ( 3 ) defines a RESURF isolation region in an n − semiconductor layer ( 2 ). A trench isolation structure ( 8 a ) and the p impurity region ( 3 ) together define a trench isolation region in the n − semiconducto...
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7439083 |
Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a verti...
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7436199 |
A stack-type semiconductor package socket may include: a first package connection portion for connection with leads of a lowermost package of a stack-type semiconductor package; a second package connection portion for connection between ...
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7435991 |
A micromechanical sensor and a method for manufacturing same are described. A secure diaphragm restraint, independent of fluctuations in the cavern etching process due to the process technology, and a free design of the diaphragm are mad...
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7435990 |
An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one ...
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7427774 |
Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the leng...
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7423288 |
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the ...
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7423287 |
The invention comprises devices and methods for determining residual stress in MEMS devices such as interferometric modulators. In one example, a device measuring residual stress of a deposited conduct material includes a material used t...
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7423286 |
The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and dielectrics, and segments of materials, such as m...
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7423282 |
A solid state electrolyte memory structure includes a solid state electrolyte layer, a metal layer on the solid state electrolyte layer, and an etch stop layer on the metal layer.
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7420206 |
A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of s...
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7419299 |
The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention provides an electronic device workpiece i...
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7418643 |
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the ...
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7418283 |
A method for quantum computing using a quantum system comprising a plurality of qubits is provided. The system can be in any one of at least two configurations at any given time including one characterized by an initialization Hamiltonia...
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7416819 |
A test mask 1 for microscopy is disclosed, which is formed on a substrate of quartz. The test mask 1 comprises a multiplicity of sub-masks 4 , which are implemented such that each sub-mask 4 comprises structures which differ withi...
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7411294 |
A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel. The circuit substrate includes an insula...
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7411210 |
A semiconductor probe with a resistive tip and a method of fabricating the semiconductor probe. The resistive tip doped with a first impurity includes a resistive region formed at a peak thereof and lightly doped with a second impurity o...
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7410837 |
A method for manufacturing a mounting substrate on which a semiconductor chip is mounted includes: forming a wiring section by electrolytic plating on a first face of a supporting substrate which is made of an insulating material, by sup...
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7408189 |
A flexible printed circuit (FPC) having testing pads thereon is provided. The FPC comprises a plurality of bonding pads and a plurality of testing pads, wherein each of the testing pads is disposed corresponding to each of the bonding pa...
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7405423 |
The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel wi...
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7400157 |
A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor dev...
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7399990 |
A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least o...
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7397260 |
A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects incl...
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7394164 |
A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of irregular bumps. The regular bumps and the ir...
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7393754 |
A tape carrier type semiconductor device comprising: a long flexible insulating tape; and a plurality of semiconductor devices sequentially arranged on one surface of the tape, wherein each semiconductor device has a wiring pattern and a...
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7393619 |
There is a structure and method for measuring the lengths of lines and spaces in semiconductor process. In an example embodiment, a lithographic structure ( 400 ) comprises, a frame ( 450 ). The frame includes a top inside edge, a top ou...
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7393471 |
An anisotropically conductive sheet which does not contaminate an object of connection, does not adhere to the object of connection even when it is left to stand for a long period of time in a state pressurized by the object of connectio...
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7391226 |
The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plural...
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7390427 |
The present invention provides an apparatus comprising a device and a mechanism for heat transfer comprising a hydrofluoroether heat-transfer fluid wherein the heat transfer fluid is represented by the following structure:
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7388385 |
A wafer is formed with metal traces that extend a distance across the wafer on opposite sides of a saw street. The resistances of the metal traces, which can each be formed from one or more layers of metal, are measured before the saw st...
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7388224 |
A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yi...
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7381986 |
An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one ...
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7375371 |
A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semi...
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7372072 |
The invention relates to a semiconductor wafer ( 1 ) having a plurality of first sawing regions ( 201 - 211 ) running parallel to one another in a first direction (X) and a plurality of second sawing regions ( 301 - 311 ) running paralle...
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7370257 |
A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits ma...
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7368749 |
A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impuri...
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7368748 |
A test pixel for use in a CMOS image sensor is employed to evaluate a pixel quality by modulating a contact chain. The test pixel for use the CMOS image sensor including: a test pixel active area corresponding to each unit pixel active a...
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7368208 |
Methods and apparatus for producing a semiconductor. A production reticle having a pattern that includes circuit features, phase shift target structures and overlay target structures is provided. The pattern is transferred multiple times...
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