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Document	Document Title
7470929	Fuse/anti-fuse structure and methods of making and programming same Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer...
7456426	Fin-type antifuse A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors...
7454104	Optical module An optical module has at least two optical elements mounted in parallel with each other. The module also has a first electrode pad which is formed between the paralleled optical elements and grounded to a ground potential and a second el...
7420204	Organic transistor An organic transistor is capable of emitting light at high luminescence efficiency, operating at high speed, handling large electric power, and can be manufactured at low cost. The organic transistor includes an organic semiconductor lay...
7372714	Methods and memory structures using tunnel-junction device as control element A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fu...
7372074	Surface preparation for selective silicon fusion bonding An apparatus and method for a silicon-based Micro-Electro Mechanical System (MEMS) device, including a pair of silicon cover structures each having a substantially smooth and planar contact surface formed thereon; a silicon mechanism str...
7358590	Semiconductor device and driving method thereof A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound ...
7327629	Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate...
7312513	Antifuse circuit with well bias transistor An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to re...
7276775	Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through...
7269898	Method for making an edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members ar...
7259427	Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate elec...
7256471	Antifuse element and electrically redundant antifuse array for controlled rupture location An antifuse element ( 102 ) having end corners ( 120, 122 ) of a gate electrode ( 104 ) positioned directly above an active area ( 106 ) or bottom electrode. The minimum programming voltage between the gate electrode ( 104 ) and the acti...
7253430	Controllable ovonic phase-change semiconductor memory device An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding fr...
7247879	Semiconductor integrated circuit device having particular testing pad arrangement In a semiconductor integrated circuit device, testing pads ( 209 b ) using a conductive layer, such as relocation wiring layers ( 205 ) are provided just above or in the neighborhood of terminals like bonding pads ( 202 b ) used only for...
7215002	Electronically programmable antifuse and circuits made therewith An antifuse device ( 120 ) that includes a bias element ( 124 ) and an programmable antifuse element ( 128 ) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antif...
7157782	Electrically-programmable transistor antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an as...
7130207	Methods and memory structures using tunnel-junction device as control element A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fu...
7126153	Organic transistor An organic transistor is capable of emitting light at high luminescence efficiency, operating at high speed, handling large electric power, and can be manufactured at low cost. The organic transistor includes an organic semiconductor lay...
7074630	Method of forming light emitter layer A light emitting layer including a quantum structure and the forming method of forming the same is provided. The forming method includes several steps. At first, a compound dielectric layer forms, including a dielectric layer and an impu...
7071534	Antifuse structure and method of use An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an ...
7053406	One-time programmable read only memory and manufacturing method thereof An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-ty...
7034328	Vertical geometry InGaN LED A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carb...
7023070	Semiconductor device The present invention prevents electrostatic discharge damage which may occur when a device chip which has a circuit with fuses mounted thereon is packaged by COG packaging, without increasing an area occupied on the device chip. The hei...
6998639	Method for manufacturing a semiconductor device A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous...
6979880	Scalable high performance antifuse structure and process Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (k eff ) such that a programming p...
6969869	Programmable resistance memory element with indirect heating The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming current to a resistor which is in therma...
6967350	Memory structures A memory structure that includes a first electrode, a second electrode, a third electrode, a control element of a predetermined device type disposed between the first electrode and the second electrode, and a memory storage element of th...
6965156	Amorphous carbon metal-to-metal antifuse with adhesion promoting layers A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an uppe...
6956278	Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is cre...
6946719	Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide ...
6943065	Scalable high performance antifuse structure and process Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (k eff ) such that a programming p...
6936909	Gate dielectric antifuse circuit to protect a high-voltage transistor According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive ...
6933591	Electrically-programmable integrated circuit fuses and sensing circuits Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) subst...
6921925	Oxygen-doped Al-containing current blocking layers in active semiconductor devices in photonic integrated circuits (PICs) In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or othe...
6919234	Method for producing an antifuse in a substrate and an antifuse structure for integration in a substrate Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the first interconnect, which end face essentially runs vertically with respect to t...
6909115	Semiconductor device applying to the crystalline semiconductor film There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction region...
6901004	High voltage switch circuitry The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes ...
6897467	Controllable ovanic phase-change semiconductor memory device An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding f...
6888215	Dual damascene anti-fuse with via before wire An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse material formed on said substrate, wherein said p...
6878614	Methods of forming integrated circuit devices including fuse wires having reduced cross-sectional areas and related structures A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so ...
6878595	Technique for suppression of latchup in integrated circuits (ICS) The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relate...
6870240	Anti-fuse and method for writing information into the anti-fuse The anti-fuse comprises a substitutable layer 14 , an interconnection layer 20 connected to the substitutable layer, and the interconnection layer contains metal atoms which can be substituted with constituent atoms of the substitutab...
6861727	Antifuse structures, methods, and applications A typical integrated circuit includes millions of microscopic transistors, resistors, and other components interconnected to define a circuit, for example a memory circuit. Occasionally, one or more of the components are defective and fa...
6861682	Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductiv...
6844609	Antifuse with electrostatic assist A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal ...
6841846	Antifuse structure and a method of forming an antifuse structure The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present invention comprises a plurality of layers, th...
6831349	Method of forming a novel top-metal fuse structure A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover the structure including a fuse region and an RDL/bump/bonding pad region. A composite me...
6831294	Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes In a semiconductor integrated circuit device, testing pads ( 209 b ) using a conductive layer, such as relocation wiring layers ( 205 ) are provided just above or in the neighborhood of terminals like bonding pads ( 202 b ) used only for...
6828652	Fuse structure for semiconductor device A fuse structure ( 30 ) formed in a semiconductor device is provided. The fuse structure ( 30 ) includes a layer of fuse material ( 32 ), a first contact ( 40 ), and a second contact ( 42 ). The first contact ( 40 ) has a first edge ( 54...

Matches 1 - 50 out of 266	1 2 3 4 5 6 >