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7449712 |
A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level...
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7427779 |
The microstructure is designed for formation of a silicon and germanium on insulator substrate of Si 1-Xf Ge Xf type, with Xf comprised between a first value that is not zero and 1. The microstructure is formed by stacking of a silicon ...
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7423283 |
Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed sili...
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7417248 |
A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous ...
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7361420 |
To provide a filmy structure of a nanometer size having a phase-separated structure effective for the case where a compound can be formed between two kinds of materials. A structure constituted by a first member containing a compound bet...
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7348598 |
A TFT, in which source and drain electrodes having concentric circular shapes are formed, reduces an OFF current caused by a leakage current and optimizes an ON current and a stray capacitance between gate and source electrodes. The TFT ...
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7341883 |
A silicon germanium (SiGe) semiconductive alloy is grown on a substrate of single crystalline Al 2 O 3 . A {111} crystal plane of a cubic diamond structure SiGe is grown on the substrate's {0001} C-plane such that a <110> orientati...
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7339188 |
The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the pol...
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7303949 |
A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:...
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7297977 |
One exemplary embodiment includes a semiconductor device. The semiconductor device comprising a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium.
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7274055 |
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form th...
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7262428 |
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically i...
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7259427 |
The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate elec...
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7259387 |
A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory el...
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7211458 |
A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from...
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7205586 |
A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. F...
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7196400 |
An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semic...
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7176504 |
A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a Si x Ge y layer and a Si x Ge y protection layer. The gate structure is deposited on the substrate and the spacer is depo...
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7176481 |
Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants impla...
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7157349 |
A method of manufacturing a semiconductor device comprising a silicon body ( 1 ) having a surface ( 4 ) provided with field isolation regions ( 2 ) enclosing active regions ( 3 ). In this method, on the surface of the silicon body there ...
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7145175 |
According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which v...
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7119369 |
A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of...
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7112836 |
A horizontal electrode having a small cross-section makes electrical contact with a chalcogenide memory element. The dimensions of the cross-section are controlled by conventional deposit/etch semiconductor processing steps. The resultin...
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7081387 |
A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls...
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7078345 |
There is disclosed a method of manufacturing a semiconductor device comprising forming a diffusion region containing arsenic impurity at a concentration of 1×10 20 cm −3 or more in an element region of Si substrate which is isolated...
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7023018 |
The present invention provides, in one embodiment, a P-type Metal Oxide Semiconductor (PMOS) device ( 100 ). The device ( 100 ) comprises a tensile-strained silicon layer ( 105 ) located on a silicon-germanium substrate ( 110 ) and silic...
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7015507 |
Provided is a non-single-crystal germanium thin film transistor having a gate insulating film capable of reducing the interface state density between an active layer and the gate insulating film. This thin film transistor has an active l...
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7009208 |
A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor po...
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7009200 |
A field effect transistor comprises a source and a drain, and a channel layer of Si 1-x-y Ge x C y crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
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7005676 |
There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si 1-x-y Ge x C y layer (1>x>0, 1>y≧0) and a peripheral region including an amorpho...
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6969878 |
A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate regi...
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6969870 |
A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the si...
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6951802 |
A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration wit...
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6936875 |
With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a dou...
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6930326 |
According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which v...
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6927417 |
In a back-surface electrode type photoelectric conversion element having electrodes and semiconductor layers for collecting carriers disposed only on a back surface side of a semiconductor substrate, a semiconductor thin film that is lar...
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6924216 |
A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a...
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6921914 |
A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si 1-x Ge x (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si 1-y Ge y layer, ...
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6885028 |
A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of whi...
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6872972 |
Roughly described, a silicon layer transitions from polysilicon at one surface to amorphous silicon at the opposite surface. The transition can be monotonic, and can be either continuous or it can change abruptly from polysilicon to amor...
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6872638 |
A method of performing irradiation of laser light is given as a method of crystallizing a semiconductor film. However, if laser light is irradiated to a semiconductor film, the semiconductor film is instantaneously melted and expands loc...
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6856002 |
The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclose...
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6855992 |
A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and ...
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6852602 |
A multi-layer film 10 is formed by stacking a Si 1-x1-y1 Ge x1 C y1 layer (0≦x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si 0.785 Ge 0.2 C 0.015 layer 13 , and a Si 1-x2-y2 Ge x2 C y2 layer (0<x2≦1 and...
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6847093 |
A semiconductor integrated circuit device is formed by a semiconductor substrate having an SiGe layer and a first Si layer epitaxially grown thereover, and on which there are element formation regions each partitioned by element isolatio...
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6838695 |
A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric laye...
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6815802 |
A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first ...
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6815269 |
A thin-film transistor is formed by a polycrystalline silicon film having a thin-film part and a thick-film part, the thin-film part minimally being used as a channel part. The polycrystalline silicon film is formed by laser annealing wi...
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6812490 |
The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemic...
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6800874 |
A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS si...
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