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Matches 1 - 50 out of 118	1 2 3 >

Document	Document Title
7423304	Optimization of critical dimensions and pitch of patterned features in and above a substrate A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above...
7400030	Schottky diode with silver layer contacting the ZnO and MgxZn1−xO films In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and Mg x Zn 1-x O epitaxial films. The ZnO and Mg x Zn 1-x O films are grown on R-plane sapphire substrates an...
7396712	Thin film processing method and thin processing apparatus A thin film processing method for processing the thin film by irradiating an optical beam to the thin film. A unit of the irradiation of the optical beam includes a first and a second optical pulse irradiation to the thin film, and the u...
7388277	Chip and wafer integration process using vertical connections A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plat...
7382035	Schottky diode with low leakage current and fabrication method thereof A low leakage Schottky diode and fabrication method thereof. The Schottky diode includes a n-type semiconductor; an anode having a circular periphery formed in a region above the n-type semiconductor; and a cathode formed in a region abo...
7378328	Method of fabricating memory device utilizing carbon nanotubes A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carb...
7354477	Method of growing GaN crystal, method of producing single crystal GaN substrate, and single crystal GaN substrate A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetition...
7348658	Multilayer silicon over insulator device An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least ano...
7303630	Method of growing GaN crystal, method of producing single crystal GaN substrate, and single crystal GaN substrate Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocat...
7250646	TFT mask ROM and method for making same There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally di...
7244666	Multi-gate transistor formed with active patterns of uniform critical dimension For fabricating a multi-gate transistor, at least one active pattern having uniform critical dimension is formed. Epitaxy structures are grown from exposed portions of the active pattern. A channel region of the transistor is formed from...
7235815	LED light set An LED light set comprising at least one LED dice and two conductive wires covered by insulated layer, a holder is installed on the wires at every certain distance, one LED dice is installed on every holder; each of the LED dice connects...
7233024	Three-dimensional memory device incorporating segmented bit line memory array A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch ...
7214963	3-D column select circuit layout in semiconductor memory devices A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between ...
7196747	Flat panel display comprising semiconductor layer with heterogeous lines Provided is a flat panel display in which no stripes appear on a screen, thereby improving image quality. The flat panel display has a matrix-type array of sub-pixels, each of which includes a driving thin film transistor, a first electr...
7193239	Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for...
7180156	Thin-film devices and method for fabricating the same on same substrate To satisfy the different requirement of TFTs function as peripheral driving circuit and pixel switching device, the modified TFT structure with various thicknesses of gate insulating layers is disclosed. For the peripheral driving circui...
7148510	Electronic apparatus having a protective circuit A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulatin...
7112826	Single crystal GaN substrate semiconductor device Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to...
7105865	AlxInyGa1−x−yN mixture crystal substrate Seeds are implanted in a regular pattern upon an undersubstrate. An Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, 0<x+y≦1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes ...
7101741	Dual double gate transistor and method for forming The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A doubl...
7042009	High mobility tri-gate devices and methods of fabrication A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substr...
7009208	Memory device and method of production and method of use of same and semiconductor device and method of production of same A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor po...
6995411	Image sensor with vertically integrated thin-film photodiode An image sensor has a vertically integrated thin-film photodiode. In one implementation, the image sensor has a substrate, an interconnection structure adjacent to the substrate, wherein the interconnection structure includes a top metal...
6992348	Semiconductor memory with vertical charge-trapping memory cells and fabrication Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provi...
6967351	Finfet SRAM cell using low mobility plane for cell stability and method for forming The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low ga...
6949768	Planar substrate devices integrated with finfets and method of manufacture A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semicond...
6933530	Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is ba...
6909132	Semiconductor device and its manufacturing method In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizi...
6909113	Three-dimensional photonic band structures in solid materials A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of space group symmetries, including a pluralit...
6906384	Semiconductor device having one of patterned SOI and SON structure A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor ...
6885031	Integrated circuit including single crystal semiconductor layer on non-crystalline layer A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline su...
6885028	Transistor array and active-matrix substrate A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of whi...
6881994	Monolithic three dimensional array of charge storage devices containing a planarized surface There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
6841813	TFT mask ROM and method for making same There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally di...
6821826	Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for t...
6815269	Thin-film transistor and method for manufacturing the same A thin-film transistor is formed by a polycrystalline silicon film having a thin-film part and a thick-film part, the thin-film part minimally being used as a channel part. The polycrystalline silicon film is formed by laser annealing wi...
6806500	Electro-optical device and electronic apparatus An electro-optical device includes a TFT array substrate, pixel electrodes, thin film transistors electrically connected to the pixel electrodes, scanning lines and data lines connected thereto, and a nitride film disposed at least on su...
6800541	Pulse laser irradiation method for forming a semiconductor thin film A method of irradiation of plural pulse laser beams onto one position of a non-single crystal semiconductor, wherein the pulse laser beams are not higher in energy density than an energy density threshold value necessary for causing a mi...
6774399	Active-matrix substrate and method of fabricating the same An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTs, gate lines, and data lines are formed on a trans...
6765229	Method for producing semiconductor device A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a cr...
6750487	Dual double gate transistor The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A doubl...
6744069	Semiconductor device and its manufacturing method Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed by performing a heat tre...
6720578	Polycrystalline silicon thin film for a thin film transistor and display device using the same A polycrystalline silicon thin film for a TFT and a display device using the same where the number of crystal grain boundaries exerts a fatal influence on movement of electric charge carrier, providing a distance “S” between active c...
6657229	Semiconductor device having multiple transistors sharing a common gate A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, wh...
6639246	Semiconductor device There is a problem in that a possibility of a carrier being caused on an interface between a semiconductor layer and an insulating film is high, and the carrier is injected into the insulating film and the interface between the insulatin...
6600173	Low temperature semiconductor layering and three-dimensional electronic circuits using the layering In a method for forming a three dimensional interconnected structure, sets of devices on receiver and donor semiconductor substrates. The donor substrate is implanted with two or more exfoliating implants, the substrates are bonded toget...
6586284	Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to...
6563134	Optoelectronic microelectronic fabrication with attenuated light leakage Within a method for fabricating an optoelectronic microelectronic fabrication, and the optoelectronic microelectronic fabrication fabricated in accord with the method, there is formed at least in part within an annular gap interposed bet...
6498372	Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer A method and structure for conductively coupling electrical structures to a semiconductor device located under a silicon on insulator (SOI) layer. The SOI layer is formed on a bulk semiconductor substrate. A trench structure through the ...

Matches 1 - 50 out of 118	1 2 3 >