This class provides for active solid-state electronic devices, that is, electronic devices or components that are made up primarily of solid materials, usually semiconductors, which operate by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action, and are not classified elsewhere.
SCOPE OF THE CLASSActive solid-state electronic devices include diodes, transistors, thyristors, etc., but exclude pure resistors, capacitors, inductors, or combinations solely thereof. The latter class of devices is characterized as passive.
The subject matter to be found here includes only active solid-state devices, per se. It may include one or more such devices combined with contacts or leads, or structures configured to be tested on a semiconductor chip, or merely semiconductor material without contacts or leads where the sole disclosed use is an active solid-state device. This subject matter does not include active solid-state devices combined with significant circuits.
Claims reciting an integrated circuit nominally with significant metallization will be classified in Class 257, whereas otherwise, nominal recitation of an integrated circuit (i.e., without significant active solid-state device recitation) will not be sufficient to permit the device to be classified in Class 257.
KEY CONCEPTSSee Subclass References to the Current Class, below, for references that relate to key concepts and terms found in Class 257. An indication that a particular concept or term occurs in one or more subclasses does not mean that the indicated subclass or subclasses are the only places that subject matter may be found. That subject matter may possibly be found elsewhere in Class 257 listed under a related term or concept that may be broader or narrower or of the same scope.
OTHER CLASSIFICATION SYSTEMSEach subclass definition may contain an OTHER CLASSIFICATION SYSTEMS listing that is to be used for informational purposes only. These classification listings may change at any time after their publication and are therefore not guaranteed to be current. In addition, the classification listing does not necessarily indicate the sole relationship between the U.
S. Patent Classification System and foreign classifications. Even where a single classification is listed for a single U.
S. subclass, a one-to-one correlation should not be inferred. As a result, information contained therein is considered to be only a guide to related subject matter.
LINES WITH OTHER CLASSESA. Classes related to Class 257 subject matter in the sense that they employ active solid-state devices in electronic circuits and the relationship of these classes to Class 257 is mainly that of a combination to a subcombination or of a genus to a specie. See References to Other Classes, below, referencing this section.
B. Classes related to Class 257 subject matter in the sense that they employ active solid-state devices in electronic circuits and the use of active solid-state electronic devices primarily as a perfecting feature. See References to Other Classes, below, referencing this section.
C. See References to Other Classes below for classes that provide for materials used in active solid-state electronic devices.
D. See References to Other Classes, below, for classes related to Class 257 because they provide for methods of making, cleaning, coating, etc., active solid-state devices, e.g., Class 438, Semiconductor Device Manufacturing: Process.
E. See References to Other Classes, below, for Classes related to Class 257 because they provide for active solid-state electronic devices structures with a specified use, e.g., Class 136, Batteries: Thermoelectric and Photoelectric.
F. See References to Other Classes, below, for classes providing for provide for subcombination subject matter that can be used as component part of active solid-state electronic devices (e.g., lead frames) or perfect the device (e.g., a heat sink).
G. Classes which provide for passive solid-state electronic devices with names that may refer to either active or passive solid-state electronic devices, e.g., coherers, varistors, varactors. luminescent or electroluminescent devices. The devices may be part of the main subject matter of the class or may be used as circuit elements in circuits or control or measuring systems which form the main subject matter of the class.
See References to Other Classes, below, referencing this section. |
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1 • BULK EFFECT DEVICE
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2 • Bulk effect switching in amorphous material
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3 • With means to localize region of conduction (e.g., "pore" structure)
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4 • With specified electrode composition or configuration
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5 • In array
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6 • Intervalley transfer (e.g., Gunn effect)
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7 • In monolithic integrated circuit
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8 • Three or more terminal device
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9 • THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)
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10 • Low workfunction layer for electron emission (e.g., photocathode electron emissive layer)
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11 • Combined with a heterojunction involving a III-V compound
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12 • Heterojunction
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13 • Incoherent light emitter
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14 • Quantum well
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15 • Superlattice
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16 • Of amorphous semiconductor material
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17 • With particular barrier dimension
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18 • Strained layer superlattice
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19 • Si x Ge 1-x
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20 • Field effect device
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21 • Light responsive structure
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22 • With specified semiconductor materials
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23 • Current flow across well
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24 • Field effect device
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25 • Employing resonant tunneling
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26 • Ballistic transport device
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27 • Field effect transistor
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28 • Non-heterojunction superlattice (e.g., doping superlattice or alternating metal and insulator layers)
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29 • Ballistic transport device (e.g., hot electron transistor)
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30 • Tunneling through region of reduced conductivity
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31 • Josephson
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32 • Particular electrode material
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33 • High temperature (i.e., >30o Kelvin)
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34 • Weak link (e.g., narrowed portion of superconductive line)
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35 • Particular barrier material
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36 • With additional electrode to control conductive state of Josephson junction
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37 • At least one electrode layer of semiconductor material
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38 • Three or more electrode device
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39 • Three or more electrode device
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40 • ORGANIC SEMICONDUCTOR MATERIAL
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41 • POINT CONTACT DEVICE
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42 • SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM
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43 • SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CuO, ZnO) OR COPPER SULFIDE
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44 • WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE
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45 • Elongated alloyed region (e.g., thermal gradient zone melting, TGZM)
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46 • In pn junction tunnel diode (Esaki diode)
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47 • In bipolar transistor structure
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48 • TEST OR CALIBRATION STRUCTURE
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49 • NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION)
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50 • Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element)
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51 • Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction)
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52 • Amorphous semiconductor material
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53 • Responsive to nonelectrical external signals (e.g., light)
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54 • With Schottky barrier to amorphous material
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55 • Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y )
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56 • With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
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57 • Field effect device in amorphous semiconductor material
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58 • With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
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59 • In array having structure for use as imager or display, or with transparent electrode
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60 • With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path)
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61 • With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain)
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62 • With impurity other than hydrogen to passivate dangling bonds (e.g., halide)
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63 • Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y )
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64 • Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation)
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65 • Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier)
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66 • Field effect device in non-single crystal, or recrystallized, Semiconductor material
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67 • In combination with device formed in single crystal semiconductor material (e.g., stacked FETs)
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68 • Capacitor element in single crystal semiconductor (e.g., DRAM)
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69 • Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., CMOS)
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70 • Recrystallized semiconductor material
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71 • In combination with capacitor element (e.g., DRAM)
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72 • In array having structure for use as imager or display, or with transparent electrode
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73 • Schottky barrier to polycrystalline semiconductor material
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74 • Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit")
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75 • Recrystallized semiconductor material
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76 • SPECIFIED WIDE BAND GAP (1.5eV) SEMICONDUCTOR MATERIAL OTHER THAN GaAsP or GaAlAs
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77 • Diamond or silicon carbide
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78 • II-VI compound
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79 • INCOHERENT LIGHT EMITTER STRUCTURE
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80 • In combination with or also constituting light responsive device
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81 • With specific housing or contact structure
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82 • Discrete light emitting and light responsive devices
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83 • Light coupled transistor structure
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84 • Combined in integrated structure
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85 • With heterojunction
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86 • Active layer of indirect band gap semiconductor
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87 • With means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in GaP)
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88 • Plural light emitting devices (e.g., matrix, 7-segment array)
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89 • Multi-color emission
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90 • With heterojunction
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91 • With shaped contacts or opaque masking
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92 • Alphanumeric segmented array
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93 • With electrical isolation means in integrated circuit structure
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94 • With heterojunction
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95 • With contoured external surface (e.g., dome shape to facilitate light emission)
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96 • Plural heterojunctions in same device
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97 • More than two heterojunctions in same device
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98 • With reflector, opaque mask, or optical element (e.g., lens, optical fiber, index of refraction matching layer, luminescent material layer, filter) integral with device or device enclosure or package
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99 • With housing or contact structure
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100 • Encapsulated
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101 • With particular dopant concentration or concentration profile (e.g., graded junction)
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102 • With particular dopant material (e.g., zinc as dopant in GaAs)
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103 • With particular semiconductor material
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104 • TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE
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105 • In three or more terminal device
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106 • Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode)
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107 • REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR)
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108 • Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal)
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109 • Having only two terminals and no control electrode (gate), e.g., Shockley diode
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110 • More than four semiconductor layers of alternating conductivity types (e.g., pnpnpn structure, 5 layer bidirectional diacs, etc.)
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111 • Triggered by V BO overvoltage means
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112 • With highly-doped breakdown diode trigger
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113 • With light activation
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114 • With separate light detector integrated on chip with regenerative switching device
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115 • With electrical trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.)
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116 • With light conductor means (e.g., light fiber or light pipe) integral with device or device enclosure or package
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117 • In groove or with thinned semiconductor portion
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118 • With groove or thinned light sensitive portion
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119 • Bidirectional rectifier with control electrode (gate) (e.g., Triac)
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120 • Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure)
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121 • With diode or transistor in reverse path
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122 • Lateral
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123 • With trigger signal amplification (e.g., amplified gate)
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124 • Combined with field effect transistor structure
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125 • Controllable emitter shunting
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126 • With means to separate a device into sections having different conductive polarity
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127 • Guard ring or groove
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128 • Having overlapping sections of different conductive polarity
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129 • With means to increase reverse breakdown voltage
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130 • Switching speed enhancement means
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131 • Recombination centers or deep level dopants
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132 • Five or more layer unidirectional structure
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133 • Combined with field effect transistor
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134 • J-FET (junction field effect transistor)
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135 • Vertical (i.e., where the source is located above the drain or vice versa)
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136 • Enhancement mode (e.g., so-called SITs)
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137 • Having controllable emitter shunt
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138 • Having gate turn off (GTO) feature
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139 • With extended latchup current level (e.g., COMFET device)
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140 • Combined with other solid-state active device in integrated structure
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141 • Lateral structure, i.e., current flow parallel to main device surface
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142 • Having impurity doping for gain reduction
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143 • Having anode shunt means
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144 • Cathode emitter or cathode electrode feature
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145 • Low impedance channel contact extends below surface
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146 • Combined with other solid-state active device in integrated structure
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147 • With extended latchup current level (e.g., gate turn off "GTO" device)
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148 • Having impurity doping for gain reduction
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149 • Having anode shunt means
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150 • With specified housing or external terminal
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151 • External gate terminal structure or composition
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152 • Cathode emitter or cathode electrode feature
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153 • Gate region or electrode feature
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154 • With resistive region connecting separate sections of device
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155 • With switching speed enhancement means (e.g., Schottky contact)
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156 • Having deep level dopants or recombination centers
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157 • With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.)
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158 • Three or more amplification stages
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159 • Transistor as amplifier
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160 • With distributed amplified current
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161 • With a turn-off diode
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162 • Lateral structure
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163 • Emitter region feature
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164 • Multi-emitter region (e.g., emitter geometry or emitter ballast resistor)
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165 • Laterally symmetric regions
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166 • Radially symmetric regions
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167 • Having at least four external electrodes
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168 • With means to increase breakdown voltage
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169 • High resistivity base layer
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170 • Surface feature (e.g., guard ring, groove, mesa, etc.)
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171 • Edge feature (e.g., beveled edge)
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172 • With means to lower "ON" voltage drop
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173 • Device protection (e.g., from overvoltage)
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174 • Rate of rise of current (e.g., dI/dt)
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175 • With means to control triggering (e.g., gate electrode configuration, Zener diode firing, dV/Dt control, transient control by ferrite bead, etc.)
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176 • Located in an emitter-gate region
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177 • With housing or external electrode
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178 • With means to avoid stress between electrode and active device (e.g., thermal expansion matching of electrode to semiconductor)
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179 • With malleable electrode (e.g., silver electrode layer)
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180 • Stud mount
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181 • With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, (e.g., ring)
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182 • With lead feedthrough means on side of housing
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183 • HETEROJUNCTION DEVICE
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183.1 • Charge transfer device
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184 • Light responsive structure
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185 • Staircase (including graded composition) device
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186 • Avalanche photodetection structure
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187 • Having transistor structure
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188 • Having narrow energy band gap (<<1eV) layer (e.g., PbSnTe, HgCdTe, etc.)
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189 • Layer is a group III-V semiconductor compound
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190 • With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch)
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191 • Having graded composition
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192 • Field effect transistor
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194 • Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))
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195 • Combined with diverse type device
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196 • Both semiconductors of the heterojunction are the same conductivity type (i.e., either n or p)
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197 • Bipolar transistor
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198 • Wide band gap emitter
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199 • Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts, including heterojunction IMPATT type microwave diodes)
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200 • Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI))
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201 • Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs
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202 • GATE ARRAYS
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203 • With particular chip input/output means
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204 • Having specific type of active device (e.g., CMOS)
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205 • With bipolar transistors or with FETs of only one channel conductivity type (e.g., enhancement-depletion FETs)
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206 • Particular layout of complementary FETs with regard to each other
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207 • With particular power supply distribution means
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208 • With particular signal path connections
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209 • Programmable signal paths (e.g., with fuse elements, laser programmable, etc)
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210 • With wiring channel area
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211 • Multi-level metallization
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212 • CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR)
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213 • FIELD EFFECT DEVICE
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214 • Charge injection device
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215 • Charge transfer device
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216 • Majority signal carrier (e.g., buried or bulk channel, or peristaltic)
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217 • Having a conductive means in direct contact with channel (e.g., non-insulated gate)
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218 • High resistivity channel (e.g., accumulation mode) or surface channel (e.g., transfer of signal charge occurs at the surface of the semiconductor) or minority carriers at input (i.e., surface channel input)
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219 • Impurity concentration variation
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220 • Vertically within channel (e.g., profiled)
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221 • Along the length of the channel (e.g., doping variations for transfer directionality)
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222 • Responsive to non-electrical external signal (e.g., imager)
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223 • Having structure to improve output signal (e.g., antiblooming drain)
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224 • Channel confinement
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225 • Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.)
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226 • Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid")
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227 • With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared)
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228 • Light responsive, back illuminated
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229 • Having structure to improve output signal (e.g., exposure control structure)
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230 • With blooming suppression structure
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231 • 2-dimensional area architecture
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232 • Having alternating strips of sensor structures and register structures (e.g., interline imager)
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233 • Sensors not overlaid by electrode (e.g., photodiodes)
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234 • Single strip of sensors (e.g., linear imager)
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235 • Electrical input
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236 • Signal applied to field effect electrode
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237 • Charge-presetting/linear input type (e.g., fill and spill)
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238 • Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback)
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239 • Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output)
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240 • Changing width or direction of channel (e.g., meandering channel)
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241 • Multiple channels (e.g., converging or diverging or parallel channels)
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242 • Vertical charge transfer
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243 • Channel confinement
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244 • Comprising a groove
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245 • Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel)
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246 • Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit")
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247 • Uniphase or virtual phase structure
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248 • 2-phase
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249 • Electrode structures or materials
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250 • Plural gate levels
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251 • Substantially incomplete signal charge transfer (e.g., bucket brigade)
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252 • Responsive to non-optical, non-electrical signal
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253 • Chemical (e.g., ISFET, CHEMFET)
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254 • Physical deformation (e.g., strain sensor, acoustic wave detector)
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255 • With current flow along specified crystal axis (e.g., axis of maximum carrier mobility)
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256 • Junction field effect transistor (unipolar transistor)
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257 • Light responsive or combined with light responsive device
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258 • In imaging array
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259 • Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor)
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260 • Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell)
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261 • Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure)
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262 • Combined with insulated gate field effect transistor (IGFET)
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263 • Vertical controlled current path
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264 • Enhancement mode or with high resistivity channel (e.g., doping of 10 15 cm -3 or less)
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265 • In integrated circuit
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266 • With multiple parallel current paths (e.g., grid gate)
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267 • With Schottky barrier gate
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268 • Enhancement mode
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269 • With means to adjust barrier height (e.g., doping profile)
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270 • Plural, separately connected, gates control same channel region
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271 • Load element or constant current source (e.g., with source to gate connection)
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272 • Junction field effect transistor in integrated circuit
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273 • With bipolar device
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274 • Complementary junction field effect transistors
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275 • Microwave integrated circuit (e.g., microstrip type)
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276 • With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge)
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277 • With capacitive or inductive elements
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278 • With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit)
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279 • Pn junction gate in compound semiconductor material (e.g., GaAs)
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280 • With Schottky gate
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281 • Schottky gate to silicon semiconductor
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282 • Gate closely aligned to source region
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283 • With groove or overhang for alignment
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284 • Schottky gate in groove
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285 • With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface)
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286 • With non-uniform channel thickness or width
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287 • With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)
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288 • Having insulated electrode (e.g., MOSFET, MOS diode)
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289 • Significant semiconductor chemical compound in bulk crystal (e.g., GaAs)
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290 • Light responsive or combined with light responsive device
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291 • Imaging array
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292 • Photodiodes accessed by FETs
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293 • Photoresistors accessed by FETs, or photodetectors separate from FET chip
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294 • With shield, filter, or lens
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295 • With ferroelectric material layer
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296 • Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)
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297 • With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)
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298 • Capacitor for signal storage in combination with non-volatile storage means
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299 • Structure configured for voltage converter (e.g., charge pump, substrate bias generator)
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300 • Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure)
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301 • Capacitor in trench
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302 • Vertical transistor
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303 • Stacked capacitor
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304 • Storage node isolated by dielectric from semiconductor substrate
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305 • With means to insulate adjacent storage nodes (e.g., channel stops or field oxide)
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306 • Stacked capacitor
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307 • Parallel interleaved capacitor electrode pairs (e.g., interdigitized)
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308 • With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post)
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309 • With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes)
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310 • With high dielectric constant insulator (e.g., Ta 2 O 5 )
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311 • Storage Node isolated by dielectric from semiconductor substrate
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312 • Voltage variable capacitor (i. e., capacitance varies with applied voltage)
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313 • Inversion layer capacitor
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314 • Variable threshold (e.g., floating gate memory device)
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315 • With floating gate electrode
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316 • With additional contacted control electrode
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317 • With irregularities on electrode to facilitate charging or discharging of floating electrode
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318 • Additional control electrode is doped region in semiconductor substrate
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319 • Plural additional contacted control electrodes
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320 • Separate control electrodes for charging and for discharging floating electrode
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321 • With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling
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322 • With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)
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323 • With means to facilitate light erasure
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324 • Multiple insulator layers (e.g., MNOS structure)
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325 • Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions)
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326 • With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure)
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327 • Short channel insulated gate field effect transistor
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328 • Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode)
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329 • Gate controls vertical charge flow portion of channel (e.g., VMOS device)
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330 • Gate electrode in groove
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331 • Plural gate electrodes or grid shaped gate electrode
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332 • Gate electrode self-aligned with groove
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333 • With thick insulator to reduce gate capacitance in non-channel areas (e.g., thick oxide over source or drain region)
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334 • In integrated circuit structure
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335 • Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)
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336 • With lightly doped portion of drain region adjacent channel (e.g., LDD structure)
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337 • In integrated circuit structure
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338 • With complementary field effect transistor
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339 • With means to increase breakdown voltage
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340 • With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode)
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341 • Plural sections connected in parallel (e.g., power MOSFET)
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342 • With means to reduce ON resistance
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343 • All contacts on same surface (e.g., lateral structure)
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344 • With lightly doped portion of drain region adjacent channel (e.g., LDD structure)
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345 • With means to prevent sub-surface currents, or with non-uniform channel doping
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346 • Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate)
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347 • Single crystal semiconductor layer on insulating substrate (SOI)
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348 • Depletion mode field effect transistor
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349 • With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate
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350 • Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.)
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351 • Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components)
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352 • Substrate is single crystal insulator (e.g., sapphire or spinel)
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353 • Single crystal islands of semiconductor layer containing only one active device
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354 • Including means to eliminate island edge effects (e.g., insulating filling between islands, or ions in island edges)
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355 • With overvoltage protective means
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356 • For protecting against gate insulator breakdown
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357 • In complementary field effect transistor integrated circuit
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358 • Including resistor element
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359 • As thin film structure (e.g., polysilicon resistor)
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360 • Protection device includes insulated gate transistor structure (e.g., combined with resistor element)
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361 • For operation as bipolar or punchthrough element
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362 • Punchthrough or bipolar element
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363 • Including resistor element
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364 • With resistive gate electrode
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365 • With plural, separately connected, gate electrodes in same device
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366 • Overlapping gate electrodes
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367 • Insulated gate controlled breakdown of pn junction (e.g., field plate diode)
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368 • Insulated gate field effect transistor in integrated circuit
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369 • Complementary insulated gate field effect transistors
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370 • Combined with bipolar transistor
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371 • Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells
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372 • With means to prevent latchup or parasitic conduction channels
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373 • With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action
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374 • Dielectric isolation means (e.g., dielectric layer in vertical grooves)
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375 • With means to reduce substrate spreading resistance (e.g., heavily doped substrate)
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376 • With barrier region of reduced minority carrier lifetime (e.g., heavily doped P+ region to reduce electron minority carrier lifetime, or containing deep level impurity or crystal damage), or with region of high threshold voltage (e.g., heavily doped channel stop region)
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377 • With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)
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378 • Combined with bipolar transistor
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379 • Combined with passive components (e.g., resistors)
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380 • Polysilicon resistor
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381 • With multiple levels of polycrystalline silicon
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382 • With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)
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383 • Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)
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384 • Including silicide
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385 • Multiple polysilicon layers
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386 • With means to reduce parasitic capacitance
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387 • Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)
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388 • Gate electrode consists of refractory or platinum group metal or silicide
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389 • With thick insulator over source or drain region
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390 • Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))
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391 • Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations)
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392 • Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode)
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393 • Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor
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394 • With means to prevent parasitic conduction channels
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395 • Thick insulator portion
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396 • Recessed into semiconductor surface
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397 • In vertical-walled groove
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398 • Combined with heavily doped channel stop portion
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399 • Combined with heavily doped channel stop portion
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400 • With heavily doped channel stop portion
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401 • With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)
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402 • With permanent threshold adjustment (e.g., depletion mode)
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403 • With channel conductivity dopant same type as that of source and drain
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404 • Non-uniform channel doping
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405 • With gate insulator containing specified permanent charge
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406 • Plural gate insulator layers
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407 • With gate electrode of controlled workfunction material (e.g., low workfunction gate material)
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408 • Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)
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409 • With means to increase breakdown voltage (e.g., field shield electrode, guard ring, etc.)
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410 • Gate insulator includes material (including air or vacuum) other than SiO 2
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411 • Composite or layered gate insulator (e.g., mixture such as silicon oxynitride)
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412 • Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)
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413 • Polysilicon laminated with silicide
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414 • RESPONSIVE TO NON-ELECTRICAL SIGNAL (E.G., CHEMICAL, STRESS, LIGHT, OR MAGNETIC FIELD SENSORS)
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415 • Physical deformation
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416 • Acoustic wave
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417 • Strain sensors
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418 • With means to concentrate stress
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419 • With thinned central active portion of semiconductor surrounded by thick insensitive portion (e.g. diaphragm type strain gauge)
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420 • Means to reduce sensitivity to physical deformation
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421 • Magnetic field
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422 • With magnetic field directing means (e.g., shield, pole piece, etc.)
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423 • Bipolar transistor magnetic field sensor (e.g., lateral bipolar transistor)
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424 • Sensor with region of high carrier recombination (e.g., magnetodiode with carriers deflected to recombination region by magnetic field)
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425 • Magnetic field detector using compound semiconductor material (e.g., GaAs, InSb, etc.)
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426 • Differential output (e.g., with offset adjustment means or with means to reduce temperature sensitivity)
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427 • Magnetic field sensor in integrated circuit (e.g., in bipolar transistor integrated circuit)
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428 • Electromagnetic or particle radiation
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429 • Charged or elementary particles
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430 • With active region having effective impurity concentration less than 10 12 atoms/cm 3
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431 • Light
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432 • With optical element
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433 • With housing or encapsulation
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434 • With window means
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435 • With optical shield or mask means
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436 • With means for increasing light absorption (e.g., redirection of unabsorbed light)
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437 • Antireflection coating
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438 • Avalanche junction
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439 • Containing dopant adapted for photoionization
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440 • With different sensor portions responsive to different wavelengths (e.g., color imager)
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441 • Narrow band gap semiconductor (<<1eV) (e.g., PbSnTe)
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442 • II-VI compound semiconductor (e.g., HgCdTe)
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443 • Matrix or array (e.g., single line arrays)
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444 • Light sensor elements overlie active switching elements in integrated circuit (e.g., where the sensor elements are deposited on an integrated circuit)
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445 • With antiblooming means
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446 • With specific isolation means in integrated circuit
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447 • With backside illumination (e.g., having a thinned central area or a non-absorbing substrate)
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448 • With particular electrode configuration
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449 • Schottky barrier (e.g., a transparent Schottky metallic layer or a Schottky barrier containing at least one of indium or tin (e.g., SnO 2 , indium tin oxide))
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450 • With doping profile to adjust barrier height
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451 • Responsive to light having lower energy (i.e., longer wavelength) than forbidden band gap energy of semiconductor (e.g., by excitation of carriers from metal into semiconductor)
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452 • With edge protection, e.g., doped guard ring or mesa structure
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453 • With specified Schottky metallic layer
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454 • Schottky metallic layer is a silicide
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455 • Silicide of Platinum group metal
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456 • Silicide of refractory metal
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457 • With particular contact geometry (e.g., ring or grid)
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458 • PIN detector, including combinations with non-light responsive active devices
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459 • With particular contact geometry (e.g., ring or grid, or bonding pad arrangement)
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460 • With backside illumination (e.g., with a thinned central area or non-absorbing substrate)
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461 • Light responsive pn junction
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462 • Phototransistor
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463 • With particular doping concentration
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464 • With particular layer thickness (e.g., layer less than light absorption depth)
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465 • Geometric configuration of junction (e.g., fingers)
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466 • External physical configuration of semiconductor (e.g., mesas, grooves)
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467 • Temperature
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468 • Semiconductor device operated at cryogenic temperature
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469 • With means to reduce temperature sensitivity (e.g., reduction of temperature sensitivity of junction breakdown voltage by using a compensating element)
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470 • Pn junction adapted as temperature sensor
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471 • SCHOTTKY BARRIER
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472 • To compound semiconductor
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473 • With specified Schottky metal
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474 • As active junction in bipolar transistor (e.g., Schottky collector)
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475 • With doping profile to adjust barrier height
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476 • In integrated structure
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477 • With bipolar transistor
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478 • Plural Schottky barriers with different barrier heights
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479 • Connected across base-collector junction of transistor (e.g., Baker clamp)
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480 • In voltage variable capacitance diode
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481 • Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts)
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