A. This class provides for manufacturing a semiconductor containing a solid-state device by a combination of operations wherein:
(1) no other class provides for the overall combination, and
(2) the intent is to use the electrical properties of the semiconductor in the device for at least one of the following purposes:
(a) conducting or modifying an electrical current,
(b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or
(c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
B. This class provides for a species of Class 427 operations involving:
(1) coating a substrate with a semiconductive material, or
(2) coating a semiconductive substrate or substrate containing a semiconductive region;wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes:
(a) conducting or modifying an electrical current,
(b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or
(c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
C. This class provides for a species of Class 216 operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region, wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes:
(1) conducting or modifying an electrical current,
(2) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or
(3) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
D. This class provides for packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor, when not elsewhere provided, wherein there are:
(1) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., mounting, housing, lead frame, discrete heat sink, etc.),
(2) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or
(3) a step of treating an already packaged semiconductor substrate (e.g., coating, etching, etc.); if the following conditions are also met:
(a) there is significant semiconductor chip structure (e.g., such as recited semiconductor junction, etc.) or named semiconductor device (e.g., DRAM, CMOS, EPROM, etc.), or
(b) there is no significant semiconductor structure if also combined with a coating operation of this class (see B above) or etching operation of this class (see C above), and
(c) the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes:
(i) conducting or modifying an electrical current, (ii) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (iii) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy;
(1) Note. When Class 438 coating (see B above) or etching operations (see C above) are not included, Class 29, following historical precedence, provides for processes of mounting, packaging, molding, or encapsulating of semiconductors having no significant semiconductor chip structure (e.g., merely recited as semiconductor chip, per se, etc.) when not elsewhere provided.
E. This is the generic class for operations not elsewhere provided for treating a semiconductive substrate or substrate containing a semiconductive region; wherein the intent is to use the semiconductor in a solid-state device for at least one of the following purposes:
(1) conducting or modifying an electrical current,
(2) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or
(3) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
(1) Note. Lacking an indication that the semiconducting material is to be used for a purpose other than
(a) conducting or modifying an electrical current,
(b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or
(c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy; it will be assumed that the process meets the Class 438 definition.
(2) Note. For this class certain materials will be considered to be semiconductors even if there is no other indication that semiconducting properties are present. Thus, if the criteria set forth under the
(1) Note is met that there is no indication that the material is to be used for a purpose other than
(a),
(b), or
(c), the following materials are to be considered semiconductive: silicon, germanium, selenium, tellurium, gallium nitride, gallium phosphide, gallium arsenide, aluminum phosphide, aluminum arsenide, and mercury cadmium telluride.
LINES WITH OTHER CLASSESSeveral classes provide for plural step operations for manufacturing semiconductor solid-state devices or components therefor. Combined operations for manufacturing semiconductor electrical devices or semiconductor-based components therefor having plural steps not encompassed by another class are proper for Class 438.
For example, while plural steps acceptable to Class 264 (e.g., injection molding and subsequent removal of flash, etc.) remain in Class 264, combinations of molding and adhesive bonding are provided for in Class 156, even though this involves multiple steps, one of which (i.e., molding) would be considered a Class 264 unit operation even if semiconductor material is involved. However, combinations of molding, adhesive bonding, and a Class 438 unit operation acting on a semiconductor substrate which is used for at least one of the following purposes:
(a) conducting or modifying an electrical current,
(b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or
(c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy, are considered proper for Class 438.
A. UNIT COATING OPERATIONS, COMBINED OPERATIONS INVOLVING COATING, AND PARTICLE BOMBARDMENTThe following search notes are intended to clarify the lines and distinctions for determining when coating operations are provided for in Class 438. Throughout this class, the term “coating” is used in the generic sense to include both surface coating and impregnation.
The unit coating operations in Class 438 may be viewed as a specie of a Class 427 process which was removed intact from Class 427 and transferred to Class 438 for the convenience of the searcher. Thus, plural step operations that were acceptable in Class 427 are now acceptable in Class 438 if the criteria for the semiconductor material as set forth hereinabove is met. Coating operations which do not meet the Class 438 definition may be classified in the classes identified in References to Other Classes, below.
B. UNIT ETCHING OPERATIONS AND COMBINED ETCHING OPERATIONS IN CLASS 438In References to Other Classes, below, are search notes are intended to clarify the lines and distinctions for determining when an etching unit operation is provided for in Class 438. Throughout this class, the term “etching” is used in the generic sense to include the removal of a surface by chemical reaction or solvent action regardless of the composition thereof.
The unit etching operations in Class 438 may be viewed as a specie of a Class 216 process which was removed intact from Class 216 and transferred to Class 438 for the convenience of the searcher. Thus, plural step operations that were acceptable in Class 216 are now acceptable in Class 438 if the criteria for the semiconductor material as set forth hereinabove is met. Etching operations which do not meet the Class 438 definition may be found in References with Other Classes, below.
C. PACKAGING (E.
G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTORPackaging is a semiconductor art manufacturing term for integration, assembly, or surrounding of a semiconductive substrate (e.g., chip, die, etc.) with a permanent encasement, housing, capsule, or support. This is distinguished from package making found in Class 53 which is directed to preparing a manufactured product for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container which is intended to be removed when the manufactured product is used.
However, other manufacturing classes have established historic lines with Class 438 that must be considered when determining proper placement. These lines with external classes revolve around such concepts as: whether there is significant semiconductor device structure, whether there is a unit operation or a so-called “multi-step” operation, etc. The search notes in References to Other Classes, below, are intended to clarify these established lines and to alert the searcher to other classes for related searches.
D. LINE NOTES TO OTHER MANUFACTURING OPERATIONSSee References to Other Classes, below for lines clarifying the relationship of other chemical classes to Class 438. For many of the chemical classes, inclusion of metal casting, working or deforming, or fusion bonding step is not acceptable if combined with an operation of the chemical class.
E. LOCATION OF SEMICONDUCTOR COMPOUND, COMPOSITION, OR STOCKAlso see References to Other Classes, below, identifying this section.
F. LINE TO HEATING CLASSESThis class (438), will take the process of
(a) heating of semiconductor material to modify the microstructure or electrical properties thereof,
(b) combined operations involving heating of semiconductor material to modify the semiconductor structure or electrical properties when not provided in another class, or
(c) heating of semiconductor substrates that affects only the nonsemiconductor region of the substrate when combined with other operations acceptable to Class 438 or combined with the establishment of device structure (e.g., connects, insulating regions, electrodes, etc.).
See References to Other Classes, below, identified as heating classes.
G. LINE NOTES TO ELECTRICAL CLASSESSee References to Other Classes, below. |
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1 • HAVING BIOMATERIAL COMPONENT OR INTEGRATED WITH LIVING ORGANISM
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2 • HAVING SUPERCONDUCTIVE COMPONENT
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3 • HAVING MAGNETIC OR FERROELECTRIC COMPONENT
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4 • REPAIR OR RESTORATION
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5 • INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION
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6 • Interconnecting plural devices on semiconductor substrate
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7 • Optical characteristic sensed
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8 • Chemical etching
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9 • Plasma etching
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10 • Electrical characteristic sensed
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11 • Utilizing integral test element
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12 • And removal of defect
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13 • Altering electrical property by material removal
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14 • WITH MEASURING OR TESTING
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15 • Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
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16 • Optical characteristic sensed
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17 • Electrical characteristic sensed
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18 • Utilizing integral test element
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19 • HAVING INTEGRAL POWER SOURCE (E.G., BATTERY, ETC.)
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20 • ELECTRON EMITTER MANUFACTURE
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21 • MANUFACTURE OF ELECTRICAL DEVICE CONTROLLED PRINTHEAD
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22 • MAKING DEVICE OR CIRCUIT EMISSIVE OF NONELECTRICAL SIGNAL
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23 • Having diverse electrical device
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24 • Including device responsive to nonelectrical signal
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25 • Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
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26 • Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
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27 • Having additional optical element (e.g., optical fiber, etc.)
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28 • Plural emissive devices
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29 • Including integrally formed optical element (e.g., reflective layer, luminescent material, contoured surface, etc.)
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30 • Liquid crystal component
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31 • Optical waveguide structure
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32 • Optical grating structure
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33 • Substrate dicing
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34 • Making emissive array
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35 • Multiple wavelength emissive
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36 • Ordered or disordered
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37 • Graded composition
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38 • Passivating of surface
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39 • Mesa formation
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40 • Tapered etching
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41 • With epitaxial deposition of semiconductor adjacent mesa
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42 • Groove formation
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43 • Tapered etching
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44 • With epitaxial deposition of semiconductor in groove
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45 • Dopant introduction into semiconductor region
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46 • Compound semiconductor
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47 • Heterojunction
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48 • MAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNAL
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49 • Chemically responsive
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50 • Physical stress responsive
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51 • Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
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52 • Having cantilever element
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53 • Having diaphragm element
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54 • Thermally responsive
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55 • Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
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56 • Responsive to corpuscular radiation (e.g., nuclear particle detector, etc.)
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57 • Responsive to electromagnetic radiation
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58 • Gettering of substrate
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59 • Having diverse electrical device
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60 • Charge transfer device (e.g., CCD, etc.)
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61 • Continuous processing
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62 • Using running length substrate
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63 • Particulate semiconductor component
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64 • Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
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65 • Having additional optical element (e.g., optical fiber, etc.)
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66 • Plural responsive devices (e.g., array, etc.)
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67 • Assembly of plural semiconductor substrates
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68 • Substrate dicing
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69 • Including integrally formed optical element (e.g., reflective layer, luminescent layer, etc.)
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70 • Color filter
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71 • Specific surface topography (e.g., textured surface, etc.)
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72 • Having reflective or antireflective component
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73 • Making electromagnetic responsive array
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74 • Vertically arranged (e.g., tandem, stacked, etc.)
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75 • Charge transfer device (e.g., CCD, etc.)
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76 • Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.)
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77 • Compound semiconductor
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78 • Having structure to improve output signal (e.g., exposure control structure, etc.)
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79 • Having blooming suppression structure (e.g., antiblooming drain, etc.)
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80 • Lateral series connected array
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81 • Specified shape junction barrier (e.g., V-grooved junction, etc.)
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82 • Having organic semiconductor component
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83 • Forming point contact
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84 • Having selenium or tellurium elemental semiconductor component
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85 • Having metal oxide or copper sulfide compound semiconductive component
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86 • And cadmium sulfide compound semiconductive component
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87 • Graded composition
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88 • Direct application of electric current
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89 • Fusion or solidification of semiconductor region
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90 • Including storage of electrical charge in substrate
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91 • Avalanche diode
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92 • Schottky barrier junction
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93 • Compound semiconductor
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94 • Heterojunction
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95 • Chalcogen (i.e., oxygen (O), sulfur (S), selenium (Se), tellurium (Te)) containing
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96 • Amorphous semiconductor
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97 • Polycrystalline semiconductor
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98 • Contact formation (i.e., metallization)
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99 • HAVING ORGANIC SEMICONDUCTIVE COMPONENT
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100 • MAKING POINT CONTACT DEVICE
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101 • Direct application of electrical current
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102 • HAVING SELENIUM OR TELLURIUM ELEMENTAL SEMICONDUCTOR COMPONENT
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103 • Direct application of electrical current
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104 • HAVING METAL OXIDE OR COPPER SULFIDE COMPOUND SEMICONDUCTOR COMPONENT
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105 • HAVING DIAMOND SEMICONDUCTOR COMPONENT
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106 • PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR
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107 • Assembly of plural semiconductive substrates each possessing electrical device
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108 • Flip-chip-type assembly
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109 • Stacked array (e.g., rectifier, etc.)
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110 • Making plural separate devices
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111 • Using strip lead frame
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112 • And encapsulating
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113 • Substrate dicing
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114 • Utilizing a coating to perfect the dicing
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115 • Including contaminant removal or mitigation
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116 • Having light transmissive window
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117 • Incorporating resilient component (e.g., spring, etc.)
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118 • Including adhesive bonding step
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119 • Electrically conductive adhesive
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120 • With vibration step
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121 • Metallic housing or support
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122 • Possessing thermal dissipation structure (i.e., heat sink)
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123 • Lead frame
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124 • And encapsulating
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125 • Insulative housing or support
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126 • And encapsulating
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127 • Encapsulating
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128 • MAKING DEVICE ARRAY AND SELECTIVELY INTERCONNECTING
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129 • With electrical circuit layout
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130 • Rendering selected devices operable or inoperable
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131 • Using structure alterable to conductive state (i.e., antifuse)
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132 • Using structure alterable to nonconductive state (i.e., fuse)
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133 • MAKING REGENERATIVE-TYPE SWITCHING DEVICE (E.G., SCR, IGBT, THYRISTOR, ETC.)
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134 • Bidirectional rectifier with control electrode (e.g., triac, diac, etc.)
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135 • Having field effect structure
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136 • Junction gate
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137 • Vertical channel
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138 • Vertical channel
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139 • Altering electrical characteristic
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140 • Having structure increasing breakdown voltage (e.g., guard ring, field plate, etc.)
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141 • MAKING CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR, ETC.)
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142 • MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS
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143 • Gettering of semiconductor substrate
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144 • Charge transfer device (e.g., CCD, etc.)
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145 • Having additional electrical device
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146 • Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.)
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147 • Changing width or direction of channel (e.g., meandering channel, etc.)
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148 • Substantially incomplete signal charge transfer (e.g., bucket brigade, etc.)
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149 • On insulating substrate or layer (e.g., TFT, etc.)
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150 • Specified crystallographic orientation
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151 • Having insulated gate
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152 • Combined with electrical device not on insulating substrate or layer
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153 • Complementary field effect transistors
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154 • Complementary field effect transistors
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155 • And additional electrical device on insulating substrate or layer
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156 • Vertical channel
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157 • Plural gate electrodes (e.g., dual gate, etc.)
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158 • Inverted transistor structure
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159 • Source-to-gate or drain-to-gate overlap
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160 • Utilizing backside irradiation
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161 • Including source or drain electrode formation prior to semiconductor layer formation (i.e., staggered electrodes)
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162 • Introduction of nondopant into semiconductor layer
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163 • Adjusting channel dimension (e.g., providing lightly doped source or drain region, etc.)
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164 • Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.)
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165 • Including differential oxidation
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166 • Including recrystallization step
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167 • Having Schottky gate (e.g., MESFET, HEMT, etc.)
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168 • Specified crystallographic orientation
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169 • Complementary Schottky gate field effect transistors
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170 • And bipolar device
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171 • And passive electrical device (e.g., resistor, capacitor, etc.)
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172 • Having heterojunction (e.g., HEMT, MODFET, etc.)
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173 • Vertical channel
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174 • Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)
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175 • Buried channel
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176 • Plural gate electrodes (e.g., dual gate, etc.)
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177 • Closed or loop gate
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178 • Elemental semiconductor
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179 • Asymmetric
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180 • Self-aligned
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181 • Doping of semiconductive region
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182 • T-gate
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183 • Dummy gate
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184 • Utilizing gate sidewall structure
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185 • Multiple doping steps
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186 • Having junction gate (e.g., JFET, SIT, etc.)
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187 • Specified crystallographic orientation
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188 • Complementary junction gate field effect transistors
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189 • And bipolar transistor
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190 • And passive device (e.g., resistor, capacitor, etc.)
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191 • Having heterojunction
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192 • Vertical channel
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193 • Multiple parallel current paths (e.g., grid gate, etc.)
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194 • Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)
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195 • Plural gate electrodes
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196 • Including isolation structure
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197 • Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)
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198 • Specified crystallographic orientation
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199 • Complementary insulated gate field effect transistors (i.e., CMOS)
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200 • And additional electrical device
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201 • Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate)
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202 • Including bipolar transistor (i.e., BiCMOS)
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203 • Complementary bipolar transistors
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204 • Lateral bipolar transistor
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205 • Plural bipolar transistors of differing electrical characteristics
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206 • Vertical channel insulated gate field effect transistor
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207 • Including isolation structure
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208 • Isolation by PN junction only
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209 • Including additional vertical channel insulated gate field effect transistor
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210 • Including passive device (e.g., resistor, capacitor, etc.)
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211 • Having gate surrounded by dielectric (i.e., floating gate)
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212 • Vertical channel
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213 • Common active region
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214 • Having underpass or crossunder
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215 • Having fuse or integral short
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216 • Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound
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217 • Doping of semiconductor channel region beneath gate insulator (e.g., threshold voltage adjustment, etc.)
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218 • Including isolation structure
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219 • Total dielectric isolation
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220 • Isolation by PN junction only
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221 • Dielectric isolation formed by grooving and refilling with dielectric material
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222 • With epitaxial semiconductor layer formation
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223 • Having well structure of opposite conductivity type
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224 • Plural wells
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225 • Recessed oxide formed by localized oxidation (i.e., LOCOS)
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226 • With epitaxial semiconductor layer formation
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227 • Having well structure of opposite conductivity type
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228 • Plural wells
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229 • Self-aligned
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230 • Utilizing gate sidewall structure
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231 • Plural doping steps
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232 • Plural doping steps
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233 • And contact formation
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234 • Including bipolar transistor (i.e., BiMOS)
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235 • Heterojunction bipolar transistor
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236 • Lateral bipolar transistor
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237 • Including diode
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238 • Including passive device (e.g., resistor, capacitor, etc.)
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239 • Capacitor
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240 • Having high dielectric constant insulator (e.g., Ta2O5, etc.)
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241 • And additional field effect transistor (e.g., sense or access transistor, etc.)
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242 • Including transistor formed on trench sidewalls
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243 • Trench capacitor
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244 • Utilizing stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.)
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245 • With epitaxial layer formed over the trench
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246 • Including doping of trench surfaces
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247 • Multiple doping steps
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248 • Including isolation means formed in trench
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249 • Doping by outdiffusion from a dopant source layer (e.g., doped oxide, etc.)
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250 • Planar capacitor
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251 • Including doping of semiconductive region
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252 • Multiple doping steps
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253 • Stacked capacitor
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254 • Including selectively removing material to undercut and expose storage node layer
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255 • Including texturizing storage node layer
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256 • Contacts formed by selective growth or deposition
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257 • Having additional gate electrode surrounded by dielectric (i.e., floating gate)
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258 • Including additional field effect transistor (e.g., sense or access transistor, etc.)
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259 • Including forming gate electrode in trench or recess in substrate
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260 • Textured surface of gate insulator or gate electrode
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261 • Multiple interelectrode dielectrics or nonsilicon compound gate insulator
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262 • Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)
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263 • Tunneling insulator
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264 • Tunneling insulator
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265 • Oxidizing sidewall of gate electrode
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266 • Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)
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267 • Including forming gate electrode as conductive sidewall spacer to another electrode
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268 • Vertical channel
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269 • Utilizing epitaxial semiconductor layer grown through an opening in an insulating layer
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270 • Gate electrode in trench or recess in semiconductor substrate
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271 • V-gate
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272 • Totally embedded in semiconductive layers
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273 • Having integral short of source and base regions
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274 • Short formed in recess in substrate
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275 • Making plural insulated gate field effect transistors of differing electrical characteristics
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276 • Introducing a dopant into the channel region of selected transistors
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277 • Including forming overlapping gate electrodes
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278 • After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.)
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279 • Making plural insulated gate field effect transistors having common active region
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280 • Having underpass or crossunder
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281 • Having fuse or integral short
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282 • Buried channel
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283 • Plural gate electrodes (e.g., dual gate, etc.)
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284 • Closed or loop gate
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285 • Utilizing compound semiconductor
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286 • Asymmetric
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287 • Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound
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288 • Having step of storing electrical charge in gate dielectric
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289 • Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)
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290 • After formation of source or drain regions and gate electrode
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291 • Using channel conductivity dopant of opposite type as that of source and drain
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292 • Direct application of electrical current
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293 • Fusion or solidification of semiconductor region
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294 • Including isolation structure
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295 • Total dielectric isolation
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296 • Dielectric isolation formed by grooving and refilling with dielectric material
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297 • Recessed oxide formed by localized oxidation (i.e., LOCOS)
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298 • Doping region beneath recessed oxide (e.g., to form chanstop, etc.)
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299 • Self-aligned
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300 • Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)
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301 • Source or drain doping
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302 • Oblique implantation
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303 • Utilizing gate sidewall structure
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304 • Conductive sidewall component
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305 • Plural doping steps
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306 • Plural doping steps
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307 • Using same conductivity-type dopant
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308 • Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.)
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309 • FORMING BIPOLAR TRANSISTOR BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS
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310 • Gettering of semiconductor substrate
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311 • On insulating substrate or layer (i.e., SOI type)
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312 • Having heterojunction
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313 • Complementary bipolar transistors
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314 • And additional electrical device
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315 • Forming inverted transistor structure
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316 • Forming lateral transistor structure
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317 • Wide bandgap emitter
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318 • Including isolation structure
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319 • Air isolation (e.g., mesa, etc.)
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320 • Self-aligned
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321 • Utilizing dummy emitter
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322 • Complementary bipolar transistors
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323 • Having common active region (i.e., integrated injection logic (I2L), etc.)
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324 • Including additional electrical device
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325 • Having lateral bipolar transistor
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326 • Including additional electrical device
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327 • Having lateral bipolar transistor
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328 • Including diode
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329 • Including passive device (e.g., resistor, capacitor, etc.)
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330 • Resistor
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331 • Having same doping as emitter or collector
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332 • Lightly doped junction isolated resistor
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333 • Having fuse or integral short
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334 • Forming inverted transistor structure
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335 • Forming lateral transistor structure
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336 • Combined with vertical bipolar transistor
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337 • Active region formed along groove or exposed edge in semiconductor
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338 • Having multiple emitter or collector structure
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339 • Self-aligned
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340 • Making plural bipolar transistors of differing electrical characteristics
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341 • Using epitaxial lateral overgrowth
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342 • Having multiple emitter or collector structure
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343 • Mesa or stacked emitter
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344 • Washed emitter
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345 • Walled emitter
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346 • Emitter dip prevention or utilization
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347 • Permeable or metal base
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348 • Sidewall base contact
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349 • Pedestal base
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350 • Forming base region of specified dopant concentration profile (e.g., inactive base region more heavily doped than active base region, etc.)
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351 • Direct application of electrical current
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352 • Fusion or solidification of semiconductor region
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353 • Including isolation structure
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354 • Having semi-insulative region
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355 • Total dielectrical isolation
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356 • Isolation by PN junction only
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357 • Including epitaxial semiconductor layer formation
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358 • Up diffusion of dopant from substrate into epitaxial layer
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359 • Dielectric isolation formed by grooving and refilling with dielectrical material
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360 • With epitaxial semiconductor formation in groove
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361 • Including deposition of polysilicon or noninsulative material into groove
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362 • Recessed oxide by localized oxidation (i.e., LOCOS)
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363 • With epitaxial semiconductor layer formation
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364 • Self-aligned
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365 • Forming active region from adjacent doped polycrystalline or amorphous semiconductor
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366 • Having sidewall
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367 • Including conductive component
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368 • Simultaneously outdiffusing plural dopants from polysilicon or amorphous semiconductor
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369 • Dopant implantation or diffusion
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370 • Forming buried region (e.g., implanting through insulating layer, etc.)
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371 • Simultaneous introduction of plural dopants
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372 • Plural doping steps
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373 • Multiple ion implantation steps
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374 • Using same conductivity-type dopant
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375 • Forming partially overlapping regions
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376 • Single dopant forming regions of different depth or concentrations
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377 • Through same mask opening
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378 • Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.)
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379 • VOLTAGE VARIABLE CAPACITANCE DEVICE MANUFACTURE (E.G., VARACTOR, ETC.)
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380 • AVALANCHE DIODE MANUFACTURE (E.G., IMPATT, TRAPPAT, ETC.)
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381 • MAKING PASSIVE DEVICE (E.G., RESISTOR, CAPACITOR, ETC.)
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382 • Resistor
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383 • Lightly doped junction isolated resistor
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384 • Deposited thin film resistor
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385 • Altering resistivity of conductor
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386 • Trench capacitor
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387 • Having stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.)
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388 • With epitaxial layer formed over the trench
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389 • Including doping of trench surfaces
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390 • Multiple doping steps
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391 • Including isolation means formed in trench
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392 • Doping by outdiffusion from a dopant source layer (e.g., doped oxide)
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393 • Planar capacitor
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394 • Including doping of semiconductive region
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395 • Multiple doping steps
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396 • Stacked capacitor
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397 • Including selectively removing material to undercut and expose storage node layer
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398 • Including texturizing storage node layer
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399 • Having contacts formed by selective growth or deposition
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400 • FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE
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401 • Having substrate registration feature (e.g., alignment mark)
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402 • And gettering of substrate
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403 • Having semi-insulating component
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404 • Total dielectric isolation
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405 • And separate partially isolated semiconductor regions
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406 • Bonding of plural semiconductive substrates
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407 • Nondopant implantation
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408 • With electrolytic treatment step
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409 • Porous semiconductor formation
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410 • Encroachment of separate locally oxidized regions
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411 • Air isolation (e.g., beam lead supported semiconductor islands, etc.)
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412 • Semiconductor islands formed upon insulating substrate or layer (e.g., mesa isolation, etc.)
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413 • With epitaxial semiconductor formation
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414 • Isolation by PN junction only
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415 • Thermomigration
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416 • With epitaxial semiconductor formation
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417 • And simultaneous polycrystalline growth
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418 • Dopant addition
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419 • Plural doping steps
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420 • Plural doping steps
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421 • Having air-gap dielectric (e.g., groove, etc.)
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422 • Enclosed cavity
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423 • Implanting to form insulator
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424 • Grooved and refilled with deposited dielectric material
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425 • Combined with formation of recessed oxide by localized oxidation
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426 • Recessed oxide laterally extending from groove
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427 • Refilling multiple grooves of different widths or depths
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428 • Reflow of insulator
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429 • And epitaxial semiconductor formation in groove
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430 • And deposition of polysilicon or noninsulative material into groove
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431 • Oxidation of deposited material
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432 • Nonoxidized portions remaining in groove after oxidation
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433 • Dopant addition
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434 • From doped insulator in groove
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435 • Multiple insulative layers in groove
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436 • Reflow of insulator
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437 • Conformal insulator formation
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438 • Reflow of insulator
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439 • Recessed oxide by localized oxidation (i.e., LOCOS)
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440 • Including nondopant implantation
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441 • With electrolytic treatment step
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442 • With epitaxial semiconductor layer formation
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443 • Etchback of recessed oxide
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444 • Preliminary etching of groove
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445 • Masking of groove sidewall
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446 • Polysilicon containing sidewall
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447 • Dopant addition
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448 • Utilizing oxidation mask having polysilicon component
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449 • Dopant addition
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450 • Implanting through recessed oxide
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451 • Plural doping steps
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452 • Plural oxidation steps to form recessed oxide
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453 • And electrical conductor formation (i.e., metallization)
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454 • Field plate electrode
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455 • BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES
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456 • Having enclosed cavity
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457 • Warping of semiconductor substrate
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458 • Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.)
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459 • Thinning of semiconductor substrate
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460 • SEMICONDUCTOR SUBSTRATE DICING
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461 • Beam lead formation
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462 • Having specified scribe region structure (e.g., alignment mark, plural grooves, etc.)
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463 • By electromagnetic irradiation (e.g., electron, laser, etc.)
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464 • With attachment to temporary support or carrier
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465 • Having a perfecting coating
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466 • DIRECT APPLICATION OF ELECTRICAL CURRENT
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467 • To alter conductivity of fuse or antifuse element
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468 • Electromigration
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469 • Utilizing pulsed current
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470 • Fusion of semiconductor region
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471 • GETTERING OF SUBSTRATE
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472 • By vibrating or impacting
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473 • By implanting or irradiating
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474 • Ionized radiation (e.g., corpuscular or plasma treatment, etc.)
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475 • Hydrogen plasma (i.e., hydrogenization)
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476 • By layers which are coated, contacted, or diffused
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477 • By vapor phase surface reaction
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478 • FORMATION OF SEMICONDUCTIVE ACTIVE REGION ON ANY SUBSTRATE (E.G., FLUID GROWTH, DEPOSITION)
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479 • On insulating substrate or layer
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480 • Including implantation of ion which reacts with semiconductor substrate to form insulating layer
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481 • Utilizing epitaxial lateral overgrowth
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482 • Amorphous semiconductor
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483 • Compound semiconductor
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484 • Running length (e.g., sheet, strip, etc.)
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485 • Deposition utilizing plasma (e.g., glow discharge, etc.)
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486 • And subsequent crystallization
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487 • Utilizing wave energy (e.g., laser, electron beam, etc.)
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488 • Polycrystalline semiconductor
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489 • Simultaneous single crystal formation
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490 • Running length (e.g., sheet, strip, etc.)
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491 • And subsequent doping of polycrystalline semiconductor
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492 • Fluid growth step with preceding and subsequent diverse operation
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493 • Plural fluid growth steps with intervening diverse operation
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494 • Differential etching
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495 • Doping of semiconductor
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496 • Coating of semiconductive substrate with nonsemiconductive material
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497 • Fluid growth from liquid combined with preceding diverse operation
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498 • Differential etching
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499 • Doping of semiconductor
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500 • Fluid growth from liquid combined with subsequent diverse operation
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501 • Doping of semiconductor
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502 • Heat treatment
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503 • Fluid growth from gaseous state combined with preceding diverse operation
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504 • Differential etching
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505 • Doping of semiconductor
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506 • Ion implantation
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507 • Fluid growth from gaseous state combined with subsequent diverse operation
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508 • Doping of semiconductor
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509 • Heat treatment
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510 • INTRODUCTION OF CONDUCTIVITY MODIFYING DOPANT INTO SEMICONDUCTIVE MATERIAL
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511 • Ordering or disordering
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512 • Involving nuclear transmutation doping
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513 • Plasma (e.g., glow discharge, etc.)
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514 • Ion implantation of dopant into semiconductor region
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515 • Ionized molecules
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516 • Including charge neutralization
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517 • Of semiconductor layer on insulating substrate or layer
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518 • Of compound semiconductor
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519 • Including multiple implantation steps
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520 • Providing nondopant ion (e.g., proton, etc.)
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521 • Using same conductivity-type dopant
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522 • Including heat treatment
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523 • And contact formation (i.e., metallization)
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524 • Into grooved semiconductor substrate region
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525 • Using oblique beam
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526 • Forming buried region
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527 • Including multiple implantation steps
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528 • Providing nondopant ion (e.g., proton, etc.)
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529 • Using same conductivity-type dopant
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530 • Including heat treatment
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531 • Using shadow mask
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532 • Into polycrystalline region
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