This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: A) components of an individual complete processor, which may be formed on a single integrated circuit (IC); B) components of a complete digital data processing system; C) plural processors; or D) plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions:
1) processing instruction data for specific processor architectures;
2) accessing or retrieving instruction data of a fixed or variable length from a buffer or other memory and shifting the instruction data to align it with a physical boundary of a buffer or other memory;
3) locating and retrieving instruction data for processing;
4) determining via internal hardware, firmware or software operations the meaning of operation codes, control bits, or operands of instruction data;
5) dispatching instruction data for execution (e.g., designating a register after resolving data conflicts);
6) dynamically testing instruction data and operands to assess conflicts related to data or hardware-resource availability (e.g., identifying data dependencies or utilization conflicts, attempting to resolve such dependencies or conflicts, or both); and
7) dynamically controlling the execution, processing, or sequencing of instruction data within a processor. |
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1 • PROCESSING ARCHITECTURE
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2 • Vector processor
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3 • Scalar/vector processor interface
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4 • Distributing of vector data to vector registers
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5 • Masking to control an access to data in vector register
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6 • Controlling access to external vector data
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7 • Vector processor operation
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8 • Sequential
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9 • Concurrent
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10 • Array processor
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11 • Array processor element interconnection
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12 • Cube or hypercube
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13 • Partitioning
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14 • Processing element memory
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15 • Reconfiguring
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16 • Array processor operation
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17 • Application specific
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18 • Data flow array processor
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19 • Systolic array processor
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20 • Multimode (e.g., MIMD to SIMD, etc.)
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21 • Multiple instruction, Multiple data (MIMD)
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22 • Single instruction, multiple data (SIMD)
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23 • Superscalar
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24 • Long instruction word
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25 • Data driven or demand driven processor
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26 • Detection/pairing based on destination, ID tag, or data
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27 • Particular data driven memory structure
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28 • Distributed processing system
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29 • Interface
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30 • Operation
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31 • Master/slave
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32 • Microprocessor or multichip or multimodule processor having sequential program control
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33 • Having multiple internal buses
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34 • Including coprocessor
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35 • Digital Signal processor
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36 • Application specific
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37 • Programmable (e.g., EPROM)
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38 • Offchip interface
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39 • Externally controlled internal mode switching via pin
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40 • External sync or interrupt signal
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41 • RISC
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42 • Operation
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43 • Mode switching
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200 • ARCHITECTURE BASED INSTRUCTION PROCESSING
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201 • Data flow based system
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202 • Stack based computer
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203 • Multiprocessor instruction
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204 • INSTRUCTION ALIGNMENT
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205 • INSTRUCTION FETCHING
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206 • Of multiple instructions simultaneously
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207 • Prefetching
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208 • INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)
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209 • Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)
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210 • Decoding instruction to accommodate variable length instruction or operand
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211 • Decoding instruction to generate an address of a microroutine
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212 • Decoding by plural parallel decoders
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213 • Predecoding of instruction component
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214 • INSTRUCTION ISSUING
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215 • Simultaneous issuance of multiple instructions
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216 • DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION
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217 • Scoreboarding, reservation station, or aliasing
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218 • Commitment control or register bypass
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219 • Reducing an impact of a stall or pipeline bubble
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220 • PROCESSING CONTROL
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221 • Arithmetic operation instruction processing
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222 • Floating point or vector
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223 • Logic operation instruction processing
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224 • Masking
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225 • Processing control for data transfer
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226 • Instruction modification based on condition
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227 • Specialized instruction processing in support of testing, debugging, emulation
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228 • Context preserving (e.g., context swapping, checkpointing, register windowing
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229 • Mode switch or change
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230 • Generating next microinstruction address
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231 • Detecting end or completion of microprogram
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232 • Hardwired controller
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233 • Branching (e.g., delayed branch, loop control, branch predict, interrupt)
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234 • Conditional branching
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235 • Simultaneous parallel fetching or executing of both branch and fall-through path
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236 • Evaluation of multiple conditions or multiway branching
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237 • Prefetching a branch target (i.e., look ahead)
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238 • Branch target buffer
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239 • Branch prediction
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240 • History table
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241 • Loop execution
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242 • To macro-instruction routine
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243 • To microinstruction subroutine
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244 • Exeception processing (e.g., interrupts and traps)
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245 • Processing sequence control (i.e., microsequencing)
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246 • Plural microsequencers (e.g., dual microsequencers)
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247 • Multilevel microcontroller (e.g., dual-level control store)
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248 • Writable/changeable control store architecture
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300 • BYTE-WORD REARRANGING, BIT-FIELD INSERTION OR EXTRACTION, STRING LENGTH DETECTING, OR SEQUENCE DETECTING
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