Title:
【発明の名称】イオンが注入された構造体および形成方法
Document Type and Number:
Japanese Patent JP2001517364
Kind Code:
A
Abstract:
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
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Inventors:
Wu, Jician
Ri
Figra, Thomas A.
Parek, Kunal Earl
Bread, Pie-Hun
Alain Earl, Rainburg
Ma, Kin Ehu
Ri
Figra, Thomas A.
Parek, Kunal Earl
Bread, Pie-Hun
Alain Earl, Rainburg
Ma, Kin Ehu
Application Number:
JP53986698A
Publication Date:
October 02, 2001
Filing Date:
March 13, 1998
Export Citation:
Assignee:
MICRON TECHNOLOGY,INC.
International Classes:
B81B3/00; B81C1/00; H01L21/02; H01L21/265; H01L21/28; H01L21/285; H01L21/306; H01L21/3205; H01L21/3213; H01L21/336; H01L21/76; H01L21/762; H01L21/768; H01L21/822; H01L21/8234; H01L21/8238; H01L21/8242; H01L23/52; H01L27/04; H01L27/088; H01L27/092; H01L27/10; H01L27/108; H01L29/78; (IPC1-7): H01L21/306; B81B3/00; B81C1/00; H01L21/265; H01L21/28; H01L21/3205; H01L21/3213; H01L21/336; H01L21/76; H01L21/768; H01L21/822; H01L21/8234; H01L21/8238; H01L21/8242; H01L27/04; H01L27/088; H01L27/092; H01L27/10; H01L27/108; H01L29/78
Attorney, Agent or Firm:
Kazuo Shamoto (5 outside)